What must be clean before a block is handed off for tapeout?
From PDVerse PnR Interview Handbook · pdVerse Mentor Guide
Short Answer
A block leaves physical verification only when every check has run on the final data and is clean or formally waived: DRC clean or waived, LVS PASS, ERC clean, antenna clean, density met, isolated vias fixed, IR drop and EM inside budget, and fill and extraction redone after the last change with timing rechecked. The order matters, because fill and ECOs change the layout; the checks must come after the last edit, not before it.
Technical Explanation
- DRC: use
signoff_check_drc(ICC2) during the fix loop, then the standaloneicv(ICV) run on the final stream as the evidence.signoff_check_drc(ICC2) runs IC Validator through ICC2 and needs an IC Validator licence; the standalone run reads the stream itself. The header incell.RESULTS(ICV) must read 'RESULTS: CLEAN', and any remaining violations must be on the approved waiver list. - LVS: the header must read 'LVS Compare Results: PASS' and 'DRC and Extraction Results: CLEAN'.
check_lvs(ICC2) in ICC2 is a routing-level check for shorts, opens and floating routes and is useful earlier, but it is not transistor-level signoff LVS. - ERC, antenna and density come from the foundry decks. Antenna is fixed during routing; the final deck proves it stayed fixed after ECOs.
- Fill and isolated vias come late, because both depend on the final routing. After fill,
signoff_fix_isolated_via -check_only true(ICC2) should report zero on every via layer. - Extraction must include the real fill, and timing must be rechecked on that extraction, since fill adds coupling capacitance.
- IR and EM:
analyze_rail -voltage_drop static -electromigration -nets {VDD VSS}(ICC2) with EM limits fromrail.tech_file(ICC2), plus dynamic analysis where the budget calls for it. Numbers are compared against the agreed budgets. - Everything must come from the same database version. Any later edit, even a single cell, restarts the relevant checks.
What To Check
- Timestamps: every report newer than the last layout edit and fill run.
- DRC and LVS headers in
cell.RESULTS(ICV), with no aborted runs. - Approved waiver list matching the remaining DRC violations one for one.
- IR and EM worst values against budget, per supply net.
- Timing on the post-fill extraction, in every signoff scenario.
Command Checks & Actions
signoff_check_drcIn-design signoff DRC on the final block through IC Validator.
check_lvs -checks {short open floating_routes}Routing-level short, open and floating check before the transistor-level LVS.
signoff_fix_isolated_via -check_only trueConfirms no isolated vias remain after the final fill.
analyze_rail -voltage_drop static -electromigration -nets {VDD VSS}Final static IR and PG EM through RedHawk Fusion.
icv -i top.gds -f GDSII -c top drc_runset.rsStandalone signoff DRC on the final stream.
icv -i top.gds -f GDSII -c top -s top.sp -sf SPICE lvs_runset.rsStandalone LVS of the stream against the SPICE netlist.
cell.RESULTSRead the header of each run before anything else.
Healthy, Suspicious & Hard-stop Results
- Healthy (illustrative): DRC 'RESULTS: CLEAN' with 3 approved waivers, LVS PASS, zero isolated vias, IR worst 34 mV against 40 mV, EM worst 87%, and timing clean on post-fill extraction.
- Suspicious (illustrative): All clean, but the DRC report is older than the last fill run, or IR and EM ran before a late ECO.
- Hard stop: LVS FAIL, DRC 'NOT CLEAN' outside the waiver list, a 'RUN ABORTED' header, IR or EM over budget, or timing never rerun after fill.
Common Mistake
The Trap: Running DRC and LVS before the final fill and a late hold ECO, and handing off with those reports. The ECO added three delay cells and the fill run reshaped metal around them, so the reports describe a layout that no longer exists. The foundry's intake run finds two spacing violations near the new cells, and the block goes back for another fill, extraction, timing and verification round.
What The Interviewer Is Testing
- Knowing the full list of checks and that they run after the last edit.
- Telling ICC2
check_lvs(ICC2) apart from signoff LVS in IC Validator. - Demanding evidence: headers, timestamps and budgets, not verbal assurances.
Follow-up Question & Model Response
"A one-cell hold fix lands after signoff. What do you rerun?"
Candidate Model Response: The layout changed, so fill near the cell is removed and repaired, and isolated vias are checked again. Extraction and timing are rerun, because the new cell and fill change the RC of nearby nets. DRC and LVS run again on a new stream, since the old reports describe a different file. IR and EM can be judged locally if the cell is small, but most teams rerun them too so every report matches the final data.
Practical Example
Tapeout Scenario: (illustrative) Exit review for a block: DRC 'RESULTS: CLEAN' with 3 approved waivers, LVS 'LVS Compare Results: PASS', antenna and density clean, isolated vias 0 on all layers, static IR worst 34 mV against 40 mV, EM worst 86%, and post-fill timing with WNS +4 ps. The reviewer notices the EM report predates a late decap ECO by one day; the rerun shows 87%, and only then is the block signed off.
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