What is the difference between Core Utilization and Local Placement Density?
From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide
Last updated:
Short Answer
Core utilization is a single chip-wide number — total cell area (standard cells plus macros) divided by total core area — and it's typically targeted around 65–75% for modern digital blocks as a static planning goal. Local placement density is a much more local, moving-window measurement: cell area inside one G-cell tile divided by that tile's area — and it can spike to 90–98% in one pocket even while 40% of the die sits completely empty.
Technical Explanation
- Core utilization is a single chip-wide number — total cell area (standard cells plus macros) divided by total core area — and it's typically targeted around 65–75% for modern digital blocks as a static planning goal.
- Local placement density is a much more local, moving-window measurement: cell area inside one G-cell tile divided by that tile's area — and it can spike to 90–98% in one pocket even while 40% of the die sits completely empty.
- That gap matters because analytical placers naturally cluster timing-critical registers tightly together, and a chip can look perfectly healthy at the global-utilization level while quietly failing at the local level.
- High local density is dangerous because it drives pin density past what the local metal layers can supply, causing G-cell overflow and unroutable shorts — the fix is to cap max density explicitly (partial blockages or placement-spacing constraints) so the placer is forced to spread cells more evenly.
Common Mistake
The Trap: Believing a chip with 50% global utilization is guaranteed to route cleanly. If the placer clusters 80% of the cells into a narrow corridor, local density exceeds 100% and routes will fail.
Follow-up Question & Model Response
"How do you limit maximum local placement density in ICC2?"
Candidate Model Response: Use set_app_options -name place.coarse.max_density -value 0.70 to cap local density across all G-cells during global placement.
Practical Example
Reporting Density & Setting Density Limits:
# Synopsys ICC2: Cap local placement density at 70%
set_app_options -name place.coarse.max_density -value 0.70
# Report density distribution map
report_placement -densityPnR Flow Mentor Guide
Master the Physical Design Implementation Flow
Read the complete 8-chapter PnR Flow Mentor Guide free on the web — library setup through placement, clock tree synthesis, routing, chip finishing, hierarchical implementation, and ECO, all the way to stream-out.
Offline PDF Bundle
Want all 1109 questions offline?
Get the complete 4-book PDF bundle (PnR, STA, MMMC, Low Power) with a clickable table of contents - no ads, no internet needed.
Continue practising