What is standard cell placement, and what are its primary goals?
From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide
Last updated:
Short Answer
Placement is the step that turns an abstract netlist ("this gate connects to that gate") into real geometry — every standard cell gets an exact (X, Y) coordinate and a legal row orientation. It's optimizing three things at once, and they pull against each other: total wirelength (measured cheaply via HPWL), timing slack under an idealized zero-skew clock, and routability — keeping local congestion from spiking anywhere.
Technical Explanation
- Placement is the step that turns an abstract netlist ("this gate connects to that gate") into real geometry — every standard cell gets an exact (X, Y) coordinate and a legal row orientation.
- It's optimizing three things at once, and they pull against each other: total wirelength (measured cheaply via HPWL), timing slack under an idealized zero-skew clock, and routability — keeping local congestion from spiking anywhere.
- It needs a locked macro floorplan, DEF row definitions, the power grid already laid down, tech LEF/cell geometry, and the SDC constraints as inputs — placement can't meaningfully start without those.
- Internally the placer works with continuous, floating-point coordinates first (global placement), then snaps everything onto the discrete row/site grid (legalization) — and throughout all of this, the clock network is still treated as an ideal, zero-delay net; CTS hasn't happened yet.
Common Mistake
The Trap: Assuming placement only cares about packing cells closely together. Blindly clustering logic creates catastrophic local pin density hotspots that cause unroutable DRC shorts during detailed routing.
Follow-up Question & Model Response
"Why does the placement engine optimize setup timing but ignore hold timing?"
Candidate Model Response: Clock trees are unbuilt and ideal during placement. Hold timing depends entirely on actual clock skew and network latency, so hold fixing is deferred to CTS and post-route.
Practical Example
EDA Command Execution:
# Synopsys ICC2: Running analytical placement and pre-CTS timing optimization
create_placement -timing_driven -congestion
place_opt
# Cadence Innovus: Global placement and pre-CTS optimization
place_opt_design -prefix pre_ctsPnR Flow Mentor Guide
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