What routing checks are specific to a power-gated domain?
From PDVerse PnR Interview Handbook · pdVerse Mentor Guide
Short Answer
In a power-gated domain you have to prove that everything that must stay alive still has power when the domain is off. That means always-on buffers and their secondary power pins routed to the always-on supply, the isolation enable and switch control nets routed correctly, and no signal from the switched domain reaching always-on logic without isolation. Standard DRC checks do not see any of this, so multivoltage checks are required.
Technical Explanation
- A power-gated domain has switches that disconnect its supply. When it is off, any cell powered by the switched supply stops working.
- Signals that must pass through or be driven inside the domain while it is off need always-on buffers, powered from the always-on supply through a secondary power pin.
- Those secondary power pins must be routed to the right supply. Zroute routes them with
route_groupon the supply net, once the pins haveis_secondary_pgandport_typeset in the frame view. - The power switch control usually runs as a daisy chain through all the switches. It must be routed as planned and powered from the always-on supply, or the domain cannot be turned on or off correctly.
- Isolation cells at the domain boundary hold outputs at a safe value when the domain is off. Their enable must be routed from always-on logic.
- No net from inside the switched domain should drive always-on logic directly.
check_mv_designchecks these multivoltage rules. - Voltage area rules can stop unrelated nets passing through the switched area, so no buffer on them ends up powered by the switched supply.
What To Check
check_mv_designfor isolation, level shifter and power intent violations.- Secondary PG pin connections on every always-on cell in the domain.
- The switch control chain, routed and connected in the planned order.
- Voltage area violations and feedthroughs from
check_routes. - Power domains and their supplies with
report_power_domains.
Command Checks & Actions
report_power_domainsLists the power domains and their supplies so you know what should connect where.
route_group -nets VDD_AONRoutes the secondary power pins of always-on cells to the always-on supply.
check_mv_designChecks multivoltage rules such as isolation and level shifting across domains.
check_routesReports voltage area violations along with DRCs and opens.
Healthy, Suspicious & Hard-stop Results
- Healthy (illustrative):
check_mv_designclean, every always-on cell's secondary pin connected, switch chain complete, no voltage area violations. - Suspicious (illustrative): A few always-on buffers added by optimization without their secondary pin routed yet, fixed with another
route_grouppass. - Hard stop: An isolation enable or switch control net driven from switched logic, or a switched-domain output reaching always-on logic without isolation.
Common Mistake
The Trap: Running route_opt late, which inserts four always-on buffers in the switched domain, and then signing off without routing their secondary power pins. Timing and DRC are clean, but those buffers have no always-on supply, so the signals they carry die whenever the domain turns off.
What The Interviewer Is Testing
- Whether you know what must stay powered and how it is connected.
- Do you check multivoltage rules, not just DRC and timing?
- A strong answer shows you re-check after optimization adds cells.
Follow-up Question & Model Response
"Why must the switch control chain itself be always-on?"
Candidate Model Response: The chain carries the signal that turns the domain's switches on and off. If it were powered by the switched supply, turning the domain off would also kill the chain, and there would be no way to turn it back on. So the buffers along the chain, and the logic driving it, are always-on cells tied to the always-on supply.
Practical Example
Tapeout Scenario: A block has one switchable domain with 48 header switches in a daisy chain, 22 isolation cells on its outputs and 9 always-on buffers inside it (illustrative). After routing, route_group -nets VDD_AON connects the 9 secondary power pins. route_opt then adds 3 more always-on buffers on a long feedthrough, connect_pg_net -automatic makes their logical PG connections, and a second route_group -nets VDD_AON connects them. check_mv_design reports one output going to an always-on block without isolation, a netlist issue sent back to the design team. After their fix, both check_mv_design and check_routes are clean.
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