BeginnerQuestion 127 of 127Source: Synopsys ICC2 Implementation User Guide: Routing

What must be clean before a routed block leaves the routing stage?

From PDVerse PnR Interview Handbook · pdVerse Mentor Guide

Short Answer

Connectivity has to be perfect: zero opens and zero shorts. DRC and antenna violations have to be zero or individually reviewed and accepted. Timing, transition, capacitance and signal integrity have to pass on routed parasitics in every active scenario, and the block has to be saved with the reports that prove it.

Technical Reference DiagramWhat must be clean before a routed block leaves the routing stage?
Exit checklist gate: zero opens and shorts, DRC and antenna reviewed, timing and SI accepted on routed parasitics in all scenarios, checkpoint saved, with one hard-stop item in red.

Technical Explanation

  • Opens and shorts are hard stops. check_routes and check_lvs both need to report zero, with check_lvs -max_errors 0 so nothing is hidden by its default cap.
  • Routing DRCs and antenna violations should be zero. If a few remain, each needs an owner and a reason, for example a known issue next to a macro that signoff DRC will judge.
  • Timing has to be checked on routed parasitics, not estimates, in every active scenario. That means setup, hold, and the logical design rules: max transition and max capacitance.
  • Signal integrity belongs in the gate: crosstalk delta delay included in timing, and noise within limits on sensitive nets.
  • Redundant via rate and any DFM steps should be complete, and routing statistics recorded.
  • Save the block with save_block along with the reports you used to decide. The next stage, and anyone debugging later, needs to know exactly what state was accepted.
  • If anything changes after this gate, such as a late ECO, the whole checklist is repeated on the new database, not just the part you think you touched.

What To Check

  • check_routes and check_lvs -max_errors 0: zero opens and shorts.
  • DRC and antenna counts, with a written disposition for anything above zero.
  • report_qor and report_constraints -all_violators in all active scenarios.
  • A saved block and its reports, stored together.

Command Checks & Actions

ICC2check_routes

Final DRC, open, antenna and voltage area check on routed signal nets.

ICC2check_lvs -max_errors 0

Final short, open and floating shape check on all nets with no reporting cap.

ICC2report_qor

Setup and hold summary across scenarios on routed parasitics.

ICC2report_constraints -all_violators

Any remaining transition, capacitance or other constraint violations.

ICC2save_block

Saves the accepted state of the block so later stages start from it.

Healthy, Suspicious & Hard-stop Results

  • Healthy (illustrative): Zero opens, shorts, DRCs and antenna violations, all scenarios passing setup, hold and DRV, block saved with reports.
  • Suspicious (illustrative): Fewer than about 10 DRCs left, each reviewed and assigned, with timing clean.
  • Hard stop: Any open or short, any scenario not analyzed, or timing only checked on estimated parasitics.

Common Mistake

The Trap: Signing off timing in the main functional scenario only. A test mode scenario was left inactive during route_opt, and it has 40 hold violations on scan paths. They are found at signoff, after the block was declared done, and fixing them reopens routing.

What The Interviewer Is Testing

  • Whether you separate hard stops from items that can be dispositioned.
  • Do you insist on routed parasitics and all scenarios?
  • A strong answer shows you keep evidence with the database.

Follow-up Question & Model Response

"Which of these items can you ever waive?"

Candidate Model Response: Opens and shorts cannot be waived; they are functional failures. A small number of routing DRCs sometimes can, if signoff physical verification shows they are false or they sit in an area owned by a macro team with a documented fix. Antenna violations can be waived only with an explicit reliability sign-off, which is rare. Timing items can be waived only with a signed-off timing exception, such as a proven false path, not because they are small.

Practical Example

Tapeout Scenario: At the exit review of a block (illustrative), check_routes shows 0 opens, 3 DRCs and 0 antenna violations. check_lvs -max_errors 0 shows 0 shorts, 0 opens and 0 floating shapes. report_qor shows all six scenarios with setup WNS above 0 and no hold violations. The 3 DRCs are end-of-line spacing at one macro pin, reviewed with the macro owner and confirmed as a known abstract issue. The block is saved with save_block along with these reports, and the next stage starts from exactly this database.

PnR Flow Mentor Guide

Read the complete 8-chapter PnR Flow Mentor Guide free on the web — library setup through placement, clock tree synthesis, routing, chip finishing, hierarchical implementation, and ECO, all the way to stream-out.

PnR Flow Physical Design Mentor Guide — eight chaptersPnR Flow Mentor GuideEight chapters, library setup through to stream-out. →