How do multi-voltage power domains (UPF) constrain standard cell placement and level-shifter positioning?
From PDVerse PnR Interview Handbook · pdVerse Mentor Guide
Short Answer
Think of a multi-voltage chip as separate mini-countries with their own currency (voltage) — a cell that belongs to the 0.75V CPU domain physically cannot live outside the CPU's voltage-area polygon, because the rows there are wired to VDD_CPU, not the top-level 0.95V rail. The voltage area is a real floorplan object the placer treats as an exclusive move bound — create_voltage_area -power_domains {PD_CPU} -region {...} — and cells mapped to that domain are hard-constrained inside it.
Technical Explanation
- Think of a multi-voltage chip as separate mini-countries with their own currency (voltage) — a cell that belongs to the 0.75V CPU domain physically cannot live outside the CPU's voltage-area polygon, because the rows there are wired to VDD_CPU, not the top-level 0.95V rail.
- The voltage area is a real floorplan object the placer treats as an exclusive move bound —
create_voltage_area -power_domains {PD_CPU} -region {...}— and cells mapped to that domain are hard-constrained inside it. - A guardband (typically ~2–5 um) surrounds each voltage area as a hard keepout, and it exists for a very physical reason: without it, adjacent N-wells at different voltages (say 0.75V vs 0.95V N-well) can short together.
- Level shifters have their own placement rule depending on the UPF strategy's
locationattribute:selfplaces them inside the destination domain's voltage area,parentplaces them in the enclosing top-level domain instead — get this wrong and you can end up with a level shifter powered by the wrong rail relative to where it's sitting. - Level shifters are dual-rail cells — they need both VDD_TOP and VDD_CPU physically routed to them, so their placement also has to respect where both supply nets are actually reachable.
- Always-On buffers are a related but separate concern: any signal that must survive a domain shutdown (like a wake-up interrupt) needs to route through AON buffers tied to a dedicated, never-shut-off VDD_AON rail — these buffers typically sit at the domain boundary they're protecting.
Common Mistake
The Trap: Placing a single-rail level shifter outside its matching voltage area, resulting in incorrect supply connections and permanent logic failure.
Follow-up Question & Model Response
"What happens if standard cells from Domain A are placed inside the Voltage Area of Domain B?"
Candidate Model Response: The tool flags a hard voltage area violation [UPF: check_mv_design], and the cells will be powered by the wrong voltage supply, leading to timing failure or electrical over-stress.
Practical Example
Voltage Area Creation & Placement Checks:
# Synopsys ICC2: Create Voltage Area polygon for CPU domain
create_voltage_area -power_domain PD_CPU -region {{100 100} {600 600}} -guardband {{2 2}}
# Multi-voltage placement legality check
check_mv_design -power_domainsPhysical Design & Planning Handbook
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