What's the actual tradeoff between fishbone, comb, and sub_strap topologies when routing to clock straps?
From PDVerse PnR Interview Handbook · pdVerse Mentor Guide
Short Answer
Fishbone (the default) connects each driver pin individually to the nearest stripe with comb routing for loads onto a single finger, controlled by -fishbone_fanout, -fishbone_span/-fishbone_sub_span, -fishbone_layers. Comb routes driver and load pins directly to the nearest stripe, falling back to Steiner topology beyond the comb distance (default 2 global routing cells) -- good for many pins directly under stripes, but creates many stacked vias, a real physical DRC risk. Sub_strap adds parallel straps on intermediate layers specifically to reduce those stacked vias versus comb.
Technical Explanation
- Fishbone (the default -topology) connects each driver pin individually to the nearest stripe, with loads comb-routed onto a single finger -- controlled by -fishbone_fanout (max loads per finger), -fishbone_span/-fishbone_sub_span (max span between loads), and -fishbone_layers.
- Comb routes driver and load pins directly to the nearest stripe; if the Manhattan distance exceeds the comb distance (default 2 global routing cells, set via route.common.comb_distance), it falls back to Steiner topology instead.
- Comb's real risk: it's suitable when many pins sit directly under mesh stripes, but it creates many stacked vias in that case -- a genuine physical DRC concern, not just a routing-quality nitpick.
- Sub_strap adds parallel straps on intermediate layers specifically to reduce stacked vias versus comb -- it requires -sub_strap_layers and has an optional -sub_strap_max_delay (default 2ps RC delay budget).
Formula Or Decision Rule
fishbone (default): individual driver connections + comb-routed loads on fingers. comb: direct-to-stripe routing, risks stacked vias. sub_strap: reduces comb's stacked-via risk via intermediate parallel straps.
What To Check
- Warning sign: physical DRC after clock strap routing shows a cluster of stacked-via violations.
- Inspect: check which -topology was used -- comb topology is the documented source of this specific risk when many pins sit directly under stripes.
- Correct: switch to sub_strap (with -sub_strap_layers configured) or fishbone if comb's stacked-via risk is the actual cause.
Command Checks & Actions
route_clock_straps -nets clk1_mesh -topology fishbone -fishbone_fanout 8Default topology with an explicit fanout limit.
route_clock_straps -nets clk1_mesh -topology combDirect-to-stripe routing, higher stacked-via risk.
route_clock_straps -nets clk1_mesh -topology sub_strap -sub_strap_layers {M5 M6}Reduces stacked vias via intermediate parallel straps.
Healthy, Suspicious & Hard-stop Results
- Expected: strap routing completes without a cluster of stacked-via DRC violations, regardless of which topology was chosen.
- Investigate: a stacked-via DRC cluster appears specifically under mesh stripes after routing -- check whether comb topology was used in that region.
- Stop: comb topology is being used across a design with many pins directly under stripes despite repeated stacked-via violations -- switch topology rather than repeatedly re-routing the same way.
Common Mistake
The Trap: Defaulting to comb topology for convenience without considering its stacked-via risk when many pins sit directly under mesh stripes -- exactly the situation where that risk is highest.
What The Interviewer Is Testing
Whether you know the real physical tradeoff (stacked vias) that distinguishes comb from the alternatives, not just that "there are three topology options."
Practical Example
Debug Scenario: Physical DRC after route_clock_straps shows a cluster of stacked-via violations concentrated where many driver pins sit directly under mesh stripes. Switching from the comb topology used there to sub_strap (with intermediate parallel straps configured via -sub_strap_layers) resolves the stacked-via concentration.
Physical Design & Planning Handbook
Master ASIC Physical Design Planning & Floorplanning
Dive into 14 comprehensive chapters covering netlist sanity, FinFET grids, macro placement, power grids, CTS, and timing budgeting.
Continue practising