What does routing do, and where does it sit in the PnR flow?
From PDVerse PnR Interview Handbook · pdVerse Mentor Guide
Short Answer
Routing turns every logical connection into real metal. Before this stage a net is only an estimate, a straight or Steiner line the tools use to guess wire length and delay. The router replaces that guess with wires on real layers, joined by vias, that obey every width and spacing rule in the technology file.
Technical Explanation
- Routing comes after placement and clock tree synthesis. By the time you start, cells have legal locations, the clock tree is built and propagated, and the power and ground network is already routed. Routing is the first step where nothing about a signal net is estimated any more.
- ICC2 runs routing through Zroute, which works in three passes: global routing picks a rough path for each net through a grid of regions, track assignment puts each segment on a real track, and detail routing draws exact metal and vias and fixes the design rule violations (DRCs) left behind.
- Clock nets are routed first, on their own rules, so they get clean resources. Signal nets follow. After that come postroute optimization, DFM steps such as redundant vias, chip finishing, and a final design rule check.
- Everything before routing leans on estimates: virtual route lengths, estimated parasitics, a congestion map. Routing replaces those with geometry. Parasitic extraction then gives real resistance and capacitance per net, and timing is rerun on those numbers.
- This is why timing often moves after routing even though no cell changed. Detours, via counts, layer choice and coupling to neighbouring wires all show up for the first time.
- What leaves the stage is a fully connected block with zero opens and shorts, DRC and antenna violations either fixed or reviewed, and timing, transition, capacitance and signal integrity accepted on routed parasitics in every scenario.
- The stage also carries manufacturing work: redundant via insertion, antenna fixing during detail routing, and wire spreading and widening for yield at the end. These belong to routing, so they are part of its exit checks.
- Routing does not rescue a bad floorplan or placement. If the congestion map before routing shows overflow, the router will spend hours in detail routing iterations and still leave DRCs. Most routing problems are cheaper to find one stage earlier, in the congestion map and
check_routability.
Common Mistake
The Trap: Treating routing as a button you press at the end. Juniors often start route_auto on a block whose global route congestion was never reviewed, then spend two days chasing thousands of detail routing DRCs in one channel. The fix was a placement or floorplan change that would have taken an hour if the congestion map had been read before routing began.
Follow-up Question & Model Response
"If placement did not change, why would setup slack get worse after routing?"
Candidate Model Response: Before routing, net delay comes from estimated wire length and estimated parasitics. After routing, each net has its real length including detours, its real layers, every via, and coupling capacitance to the wires next to it. A net that detours around a macro or picks up a long parallel neighbour gets slower. Crosstalk can also add delta delay that did not exist in the preroute estimate. The slack change comes from replacing the estimate with the routed wire.
Practical Example
Tapeout Scenario: A 1.2 mm by 0.9 mm block reaches routing with setup WNS of -8 ps on estimated parasitics (illustrative). Clock nets are routed first with a double-width rule, then signal nets with route_auto. After extraction the worst path moves to -31 ps because one net detours 140 um around a memory macro and runs next to a busy bus for most of that length. Postroute optimization resizes the driver and adds one buffer, and the path closes at +4 ps.
PnR Flow Mentor Guide
Master the Physical Design Implementation Flow
Read the complete 8-chapter PnR Flow Mentor Guide free on the web — library setup through placement, clock tree synthesis, routing, chip finishing, hierarchical implementation, and ECO, all the way to stream-out.
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