Why is physical signoff so strict? What does a missed defect cost?

Short Answer

Once masks are made, the layout cannot be patched: a defect that escapes means new masks, a new wafer run and months before corrected silicon is back. Advanced-node mask sets are very expensive, and the schedule loss often costs more than the masks because the product misses its market window. So physical signoff treats every unexplained DRC, LVS, ERC, IR or EM result as a blocker until it is fixed or formally waived.

Technical Explanation

• The cost of a defect grows with each stage it survives. In ICC2 it costs minutes to hours; at foundry intake the database is rejected and days are lost; after mask making the affected masks are redone; after first silicon there is debug on top of a respin; in the field there are returns.
• Each escape type fails differently. A DRC escape lowers yield or makes a layer unbuildable. An LVS escape, a short or open, breaks function. An ERC escape such as a floating gate adds leakage or random behaviour. IR escapes cause speed failures, and EM escapes cause failures after months of use, the hardest kind to trace.
• DRC decks encode yield. Rules are the foundry's prescription for masks, and insufficient DRC coverage can lead to low yield or no yield at all.
• A metal-only fix is cheaper because the base layers are reused, which is why spare cells exist. It still needs new metal masks, a wafer run and full re-verification.
• Strict does not mean zero exceptions. It means every exception is written down, reviewed and accepted by the foundry or owner as a waiver, with a reason. An unexplained violation is never a waiver.
• Signoff must run on the final data. Any change after the last run, even a one-cell ECO, invalidates the results for the area it touches, and usually for the whole block because fill and extraction change with it.
• Tool status must be read, not assumed. A run that ends in 'RESULTS: RUN ABORTED' in cell.RESULTS (ICV) has proved nothing, even if it produced no error list.
• The checks are cheap compared with what they prevent. A full DRC and LVS run takes hours of machine time, while a respin takes months of calendar time and the whole team's attention, so running one more check is almost always the right call when in doubt.

Follow-up Question & Model Response

"What is a metal-only ECO, and why doesn't it make strict signoff unnecessary?"

Candidate Model Response: A metal-only ECO changes only metal and via layers, often by rewiring spare cells that were placed before tapeout. The transistor layers are reused, so it is cheaper and faster than a full respin. It still needs new metal masks, a new wafer run and weeks to months of schedule. It also must pass the same DRC, LVS and electrical checks, because a mistake in the ECO leads to yet another respin.