What's the practical difference between timing with a wire-load model and timing with real layout data?

Short Answer

A zero wire-load model means pre-layout, zero net delays -- cell propagation delays only, useful early but unrealistic. A real wire-load model estimates loading/delay effect of fanout from the technology library (an area-based default) -- better than zero, still an estimate. Post-layout extracted-parasitics STA, using actual LEF/routing data, is far more accurate and meaningfully reduces timing closure surprises later in the flow.

Technical Explanation

• A zero wire-load model assumes pre-layout, zero net delays -- only cell propagation delays are counted. Useful very early, but unrealistic once real interconnect exists.
• A real wire-load model estimates the loading/delay effect of fanout from the technology library (an area-based default) -- a step up from zero, but still an estimate, not measured data.
• Post-layout extracted-parasitics STA, using actual LEF/routing data, is far more accurate and meaningfully reduces timing closure surprises later in the flow.
• Timing analysis is done either with wire-load models during synthesis, or by feeding actual layout information to the analyzer -- these are genuinely different accuracy tiers, not interchangeable.
• The two modes have distinct real commands: set_wire_load_model for the pre-layout estimate, versus extract_rc (post-layout SPEF-based parasitics) once real routing exists.

Follow-up Question & Model Response

"Given post-layout timing is more accurate, why would a flow ever deliberately use a wire-load model instead?"

Candidate Model Response: Because early in the flow (pre-placement, pre-routing) there simply is no real layout data yet to extract parasitics from -- a wire-load model is the only option available at that stage, used specifically for early estimation, not as a substitute for post-layout signoff timing.