How do you constrain a port that receives paths from multiple clocks, and why is -add_delay needed?
From PDVerse PrimeTime STA Interview Guide · pdVerse Mentor Guide
Ten-second Interview Answer
Specify each clock's delay on the port with -add_delay . Without it, a new set_input_delay or set_output_delay removes the existing delay data on that port and replaces it, so the second command would wipe out the first clock's budget.
Complete Technical Explanation
When paths from more than one clock, or from more than one edge, arrive at the same port, each needs its own budget on that port - and the mechanism for accumulating them is -add_delay . The reason it is mandatory rather than stylistic is the default behaviour: without -add_delay, a new set_input_delay or set_output_delay on a port removes the existing delay data there and replaces it. So specifying a second clock's delay without the option does not add a second budget, it silently discards the first. With -add_delay, the new delay sits alongside the existing ones and the port ends up constrained relative to all the relevant clocks. For example, set_input_delay 4.5 -clock PHI1 {IN1} followed by set_input_delay 2.3 -clock PHI2 -add_delay {IN1} gives IN1 delays relative to both PHI1 and PHI2, whereas set_input_delay 2.3 -clock PHI2 {IN1} would have removed the PHI1 delay. The same applies to edges of one clock: set_input_delay 4.5 -clock PHI1 -max -rise -add_delay {IN1} and set_input_delay 4.0 -clock PHI1 -max -fall -add_delay {IN1} accumulate rather than overwrite. This matters whenever a port genuinely receives data launched by different clocks, or on different edges, in different modes or paths - each launching condition needs its own budget.
In Pd / Signoff
You hit this on any interface fed from two source domains or characterized separately for rise and fall. The check is report_port: it should list every delay you intended on the port. If only the last-specified clock appears, the earlier ones were overwritten and their paths are now mis-budgeted or unconstrained.
Common Trap
Omitting -add_delay on the second and subsequent commands. The first clock's delay is removed with no error, so the PHI1 paths become unconstrained or mis-budgeted while the port still looks constrained - a silent under-constraint that produces no violations rather than wrong ones.
Expect Next
When does a port legitimately need input delays from more than one clock?
Topic And Primetime Commands
Constraints / I/O Timing. set_input_delay, set_output_delay, add_delay, report_port
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