Why must a generated clock's master clock be named explicitly with -master_clock when its source pin receives multiple clocks?

Short Answer

create_generated_clock normally figures out the master clock on its own, by finding whichever clock reaches the named -source pin. When more than one clock can reach that pin — a multiplexed clock source feeding a shared divider, for example — that inference becomes ambiguous, and -master_clock has to name the intended clock explicitly.

Technical Explanation

A generated clock's -source pin can, in some designs, have more than one clock reaching it, and the tool needs to know which one is the real master.

• create_generated_clock -source [get_pins DIV1/CP] (SDC) normally infers the master clock automatically from whichever clock the tool finds propagating to that source pin.
• Some pins genuinely receive more than one clock, for example a multiplexed clock source feeding a divider that is shared between two operating modes, each with its own upstream clock.
• When more than one clock reaches the source pin, the inference becomes ambiguous, and the tool needs an explicit -master_clock (SDC) argument alongside -source to say which of the candidate clocks the generated clock actually derives from.
• Without -master_clock in that ambiguous case, the command can fail outright or silently pick an unintended clock, producing a generated clock with the wrong period or phase relationship.
• report_clock (PT) is the way to confirm the tool resolved it correctly, since that report names the generated clock's actual master clock and master source pin, letting you check it against what you intended.
• Why it matters: this situation is common in designs with clock muxes feeding a shared divider — leaving -master_clock out is a routine oversight there, and the resulting misidentified generated clock can carry through the whole downstream timing model until someone notices the report looks wrong.

Follow-up Question & Model Response

A clock mux MUX1 selects between CLK_A and CLK_B feeding a shared divider flip-flop, DIV1. How do you make sure the generated clock off DIV1 is correctly tied to CLK_A in the mode where CLK_A is selected?

Candidate Model Response: I would write create_generated_clock -source [get_pins DIV1/CP] -master_clock [get_clocks CLK_A] -divide_by 2 -name DIV_A [get_pins DIV1/Q] (SDC), explicitly naming CLK_A as the master rather than relying on the tool to infer it from the mux's two candidate inputs. I would define a separate generated clock for the CLK_B case the same way, each active in its own mode-specific scenario, and then confirm with report_clock [get_clocks DIV_A] (PT) that the master clock and master source pin match what I intended for each mode.