How would you constrain a design for both setup and hold analysis at the boundary?
From PDVerse PrimeTime STA Interview Guide · pdVerse Mentor Guide
Ten-second Interview Answer
Specify both -max and -min input and output delays at every boundary port. Setup analysis uses the maximum late external delays and hold uses the minimum early ones, so constraining only one leaves the other check unbudgeted.
Complete Technical Explanation
Setup and hold are separate checks that consume different extremes of the external delay range, so the boundary has to supply both. On inputs, set_input_delay -max gives the maximum external delay, which feeds the setup check on the internal path starting at that input, and -min gives the minimum external delay, which feeds the hold check. A single value typically applies to both, but for accurate analysis you set the max and min external delays separately, because the real external path has a range and the two values genuinely differ. On outputs, set_output_delay -max gives the longest external path plus the external register's setup, which feeds the setup check on the internal path ending at that output, and -min gives the shortest external path minus hold, feeding the hold check. Drive and load are set for the min and max corners as appropriate. The reasoning is that setup checks whether the latest-arriving data still meets the capture register's setup requirement, so it uses the maximum delays throughout, while hold checks the earliest arrival against the hold requirement and uses the minimum delays. The completeness consequence is the part people miss: both min and max at every boundary port, or the setup or hold check on those paths is incomplete. Set only -max and the hold paths from and to that port have no early external budget, so they are effectively unconstrained for hold.
In Pd / Signoff
This is a boundary-completeness audit you run before hold closure, typically right after CTS when hold becomes the live problem. You confirm from report_port that every port has both a min and a max delay in each applicable direction, because a max-only interface will report clean hold at the boundary regardless of what the silicon does.
Common Trap
Specifying only -max delays because setup is what everyone is watching. The hold paths from and to those ports then carry no early external budget and are silently unchecked, so a real hold violation at the interface never appears - and hold failures are the ones you cannot work around after fabrication.
Expect Next
Which delay, min or max, feeds the setup check, and which feeds hold?
Topic And Primetime Commands
Constraints / I/O Timing. set_input_delay, set_output_delay, report_port
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