Explain how MIS, CRPR, and the hold check interact on a short clock-adjacent data path.
From PDVerse PrimeTime STA Interview Guide · pdVerse Mentor Guide
Ten-second Interview Answer
All three land on min delay. MIS speeds up co-switching data gates so data arrives earlier, which tightens hold; CRPR removes shared-clock-segment pessimism from the launch and capture timing; the hold check then compares the MIS-shortened arrival against the CRPR-adjusted capture.
Complete Technical Explanation
Three effects converge on the same quantity -min delay, which is what the hold check consumes. MIS reduces data-path gate delays wherever multiple inputs co-switch, the Case-B speed-up, and the consequence is that data arrives earlier. Earlier data is the dangerous direction for hold, so MIS tightens the check. CRPR works on the clock side: it removes the pessimism of treating the shared segment of the launch and capture clock paths as independent, adjusting the launch and capture timing on the common portion, and for a zero-cycle hold check it also reconciles crosstalk on that common segment. The hold check then compares the MIS-shortened min data arrival against the CRPR-adjusted capture time. The subtlety worth voicing is that the two effects do not push the same way. MIS makes data faster and so tightens hold unambiguously; CRPR removes launch and capture pessimism, which can loosen or tighten hold depending on the shared segment. Both therefore have to be modelled to get the true hold margin. Leave MIS out and you are optimistic, because data really can arrive earlier than you modelled. Mishandle CRPR and you carry false pessimism instead. On a short clock-adjacent path where a few picoseconds decide the verdict, getting both right is precisely what separates a real hold violation from a phantom - which is why MIS is scoped to hold in the first place and why CRPR has a specific zero-cycle crosstalk rule.
In Pd / Signoff
This is a post-route hold-signoff debug situation. On a short path that fails hold by picoseconds, you check that MIS is active on the data gates and that CRPR is enabled with its zero-cycle crosstalk handling, then read the launch and capture clock legs to see how much common-path credit was applied. The decision it drives is whether to spend a hold buffer or dismiss the violation as pessimism.
Common Trap
Disabling MIS to make a short hold path pass, or crediting CRPR without checking the zero-cycle crosstalk treatment on the common segment. Turning MIS off is optimistic - real data can arrive earlier than the model - while a mishandled CRPR leaves false pessimism that gets paid for in unnecessary hold buffers.
Expect Next
On a zero-cycle hold check, why does crosstalk on the common clock segment need reconciling rather than simply cancelling out?
Topic And Primetime Commands
Delay Calculation / Interconnect & Ceff. No specific PrimeTime command is required for this conceptual answer.
Keep building interview depth
Continue practising STA
Continue learning free
Get a practical low-power chapter
Receive the existing “Low Power and Multivoltage Fundamentals” PDF chapter and its download link by email.
Continue practising