Explain why set_voltage's max-delay number is the lower voltage in a corner pair, connecting it to STA fundamentals.
From PDVerse PrimeTime STA Interview Guide · pdVerse Mentor Guide
Ten-second Interview Answer
Max-delay means worst setup, worst setup means slowest cells, and cells are slowest at low voltage because there is less drive current. So the max-delay number is the low corner and the -min number is the high one.
Complete Technical Explanation
The confusion comes from reading max-delay as max-voltage, and the fix is to walk the chain deliberately. Max-delay analysis exists to catch setup failures, and setup failures happen when cells are slow. Cells are slowest at low voltage, because lower supply means less drive current and therefore longer delays. So the voltage that produces max delay is the low corner. Run the same logic for the other side: min-delay analysis catches hold failures, hold failures happen when cells are fast, and cells are fastest at high voltage - so the min-delay voltage is the high corner. That is why an example like set_voltage 0.8 -min 1.2 VDD is correct even though it looks backwards, with the bare number smaller than the -min number. The bare number is the max-delay voltage, 0.8, the slow corner. The -min value, 1.2, is the min-delay voltage, the fast corner. The single sentence worth carrying into an interview is max-delay equals worst setup equals slow equals low voltage. Once you have that, the apparent inversion stops being something to memorize. Note also what the mapping actually is: max-delay and min-delay map to slow and fast, not to numerically high and low. That distinction matters because inverted-temperature behavior or specific corner definitions can complicate which numeric value ends up where, while the delay-role mapping holds.
In Pd / Signoff
Every multivoltage set_voltage line you write depends on getting this straight, and it is the first thing to check when reviewing someone else's constraint file. If the bare value is the higher number, setup is being analyzed at the fast corner and hold at the slow one - both optimistic. A quick report_timing -voltage on a setup path should show the low corner voltage on the cells; if it shows the high one, the set_voltage arguments are swapped.
Common Trap
Reading max-delay as max-voltage and writing set_voltage 1.2 -min 0.8 VDD, which analyzes setup at the fast corner and hold at the slow corner. Nothing errors and both checks look comfortable, because each is being run at exactly the voltage that makes it easy to pass.
Expect Next
Does that mapping always put the numerically lower voltage on the max-delay side, or can corner definitions and inverted-temperature behavior break the numeric pattern while the slow/fast roles hold?
Topic And Primetime Commands
Multivoltage / General. set_voltage, report_timing
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