What are PVT corners, and why does timing change across them?
From PDVerse STA Mentor Guide · pdVerse Mentor Guide
Short Answer
PVT corners refer to combinations of Process, Voltage, and Temperature conditions at which a standard cell's timing is characterized. A library is not one single file, it ships as a set of files, one per PVT condition.
Example
Each of these separate library files represents the cell's timing data as characterized at that specific process/voltage/temperature combination, rather than a single 'typical' snapshot.
Why It Matters
A real chip does not always run at exactly the same manufacturing process point, supply voltage, and temperature; these vary from chip to chip and moment to moment. Because cell delay actually shifts under different PVT conditions, you need separate characterized data for each corner so STA can check timing under the worst-case (and best-case) realworld conditions the chip might experience.
Mentor Note — Common Mistake
Don't assume a single library run at 'typical' conditions is enough to sign off a design. Each PVT corner can shift delays differently, so multiple corners must be checked.
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