IntermediateQuestion 43 of 112Source: Synopsys PrimeTime User Guide: Hold Timing Checks

How can clock skew alone create a hold violation, even with zero logic delay?

From PDVerse STA Mentor Guide · pdVerse Mentor Guide

By Tabish Iqbal · 9+ Years VLSI Physical Design Experience

Short Answer

A hold check compares how fast new data can race through the logic against how much extra time the clock gives the capturing flip-flop before its next edge. If the capturing flop's clock edge arrives earlier than the launching flop's edge — negative skew from the capture side's point of view — that time budget can go negative even when there is almost no logic delay to eat into it at all.

A two-flop reg2reg diagram with near-zero logic delay, showing the capture flop's clock branch 55ps shorter than the launch flop's branch, turning a 40ps nominal hold margin into a -15ps violation. — Technical Reference DiagramHow can clock skew alone create a hold violation, even with zero logic delay?

Technical Explanation

Hold time is about the minimum path, and skew shifts that minimum requirement directly.

Hold slack is capture edge time minus (launch edge time plus data arrival plus hold requirement). With zero logic delay, data arrival is essentially the clock-to-Q delay of the launching flop alone.
If both clocks arrive at the same time, there is usually a comfortable margin, because clock-to-Q delay is normally larger than the flop's own hold-time requirement.
Skew shifts one side of that equation. If the capturing flop's clock edge physically arrives earlier than the launching flop's edge — for example, the capture flop sits on a shorter clock-tree branch — the capturing flop needs the new data to be stable sooner, tightening the margin.
Enough skew erases the margin entirely. Once the skew exceeds the difference between clock-to-Q delay and the hold requirement, the hold check goes negative, with no logic delay involved at all.
This is why hold violations cluster at low-latency, low-logic paths. A reg2reg path with almost no combinational logic between two flops on the same clock has the least margin to spare, so it is the first place skew-driven hold failures show up.
The fix is skew reduction or added delay, not logic changes, since the problem is entirely on the clock side — a small buffer inserted in the data path, or clock-tree rebalancing, both restore the margin.

Common Mistake

The Trap: assuming a hold violation always points to a data path that is too fast and needs a buffer, without first checking clock skew.

Engineers sometimes add a data-path delay buffer as a reflex fix, which does work, but if the real cause is a large skew imbalance, the same skew will threaten other nearby paths that a single local buffer does not address.
Fixing skew at the clock-tree level, when that is the actual cause, resolves the whole cluster of nearby hold-marginal paths at once instead of patching them one at a time.

Follow-up Question & Model Response

You find ten hold violations, all between flops driven by the same two clock-tree branches. Would you fix each path individually?

Candidate Model Response: Not as the first move. Ten violations concentrated between the same two branches strongly suggests a shared skew problem between those branches rather than ten unrelated data-path issues. I would pull report_clock_timing (PT) for both branches to confirm the skew value and compare it against the flops' hold-time requirement and clock-to-Q delay. If the skew explains most of the shortfall, I would ask the clock-tree team to rebalance that branch pair first, then re-run hold analysis — that single fix likely clears most or all ten violations, whereas ten individual data-path buffers would each add area and only patch the symptom.

Practical Example

Two flops on the same 800MHz clock domain sit directly next to each other with essentially zero combinational logic between them. The launching flop has a clock-to-Q delay of 80ps and the flop's hold-time requirement is 40ps, leaving a nominal 40ps margin if both clocks arrive together. Post-CTS, report_clock_timing (PT) shows the capturing flop's branch is 55ps shorter than the launching flop's branch — 55ps of skew working against hold. The path fails hold by -15ps (40ps margin minus 55ps skew) despite having almost no logic delay at all. A clock-tree rebalance that trims the skew to 25ps brings the path back to +15ps hold slack.

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