IntermediateQuestion 44 of 112Source: Synopsys PrimeTime User Guide: Multiple Clock Timing Relationships

What is the difference between an intra-clock path and an inter-clock path in STA, and why does the tool treat them differently?

From PDVerse STA Mentor Guide · pdVerse Mentor Guide

By Tabish Iqbal · 9+ Years VLSI Physical Design Experience

Short Answer

An intra-clock path starts and ends on flip-flops driven by the same clock, so the launch and capture edges come from one predictable waveform. An inter-clock path crosses from one clock to a different clock, so the tool has to reason about the relationship — or lack of one — between two separate waveforms before it can even define what a valid launch-to-capture edge pair looks like.

Technical Reference DiagramWhat is the difference between an intra-clock path and an inter-clock path in STA, and why does the tool treat them differently?
Two stacked clock waveforms, a 4ns period and a 6ns period, aligned over their 12ns least-common-multiple window, with the worst-case launch-to-capture edge pair marked and labeled against a single-clock waveform for comparison.

Technical Explanation

The distinction matters because it decides which edges the tool is even allowed to pair up.

  • Intra-clock paths use one waveform for both ends. The setup check pairs a launch edge with the very next capture edge of the same clock, and skew comes only from clock-tree delay differences, not from any relationship between two separate clocks.
  • Inter-clock paths need a defined relationship between two clocks first. If both clocks come from create_clock (SDC) with related periods — say one is twice the frequency of the other — the tool can compute a common repeating pattern and find the worst-case edge pairing across that pattern.
  • If the two clocks are unrelated, the tool still times the path by default, picking some worst-case alignment unless told otherwise — why undeclared crossings can produce a false violation.
  • This is exactly why set_clock_groups -asynchronous (SDC) exists. Declaring two clocks asynchronous tells the tool to stop timing paths between them entirely, rather than reporting a misleading worst-case number for a relationship that does not really exist in silicon.
  • Why it matters: treating every inter-clock path the same way as an intra-clock path — assuming a fixed, simple edge relationship — is one of the most common sources of over- or under-constraining a design.

Common Mistake

The Trap: assuming an inter-clock path is timed the same way as a same-clock path, just with two different clock names in the report.

  • A designer looks at a setup violation between two related clocks and expects the fix to be identical to a same-clock violation — resize a cell, add a buffer — without checking for an unintended edge alignment.
  • If the two clocks are actually meant to be unrelated in silicon (say, driven by separate, unsynchronized oscillators), leaving them untagged lets the tool report a false violation based on a coincidental worst-case alignment that will never occur in practice.

Follow-up Question & Model Response

A path between two clocks with periods 4ns and 6ns fails setup by 200ps. Is that the same kind of failure as a same-clock setup violation?

Candidate Model Response: Structurally yes — it is still required time minus arrival time going negative — but the required time comes from a different place: the tool finds the repeating pattern across the two periods' least common multiple, 12ns, and checks every valid edge pair within that window. Before treating it like an ordinary same-clock fix, I would confirm the two clocks are genuinely meant to have a fixed frequency relationship in silicon — if they are actually unrelated or asynchronous in the real design, the correct fix is set_clock_groups -asynchronous (SDC) to remove the check, not a data-path buffer to satisfy a timing relationship that should not exist.

Practical Example

A design has CLK_A at 4ns and CLK_B at 6ns, both derived from the same PLL with a known, intended 2:3 frequency relationship. A path from CLK_A to CLK_B fails setup by 200ps at one specific edge alignment within the 12ns combined pattern (the LCM of 4ns and 6ns). Because the relationship is real and intended, the team fixes it with a data-path buffer, the same way they would for a same-clock violation. In a separate case on the same chip, a path between CLK_A and an unrelated test-mode clock CLK_T shows a similar-looking violation — but since CLK_T is only active during a separate test mode never active alongside CLK_A, the team applies set_clock_groups -asynchronous (SDC) instead, removing the false check entirely.

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