How does a SPEF corner differ from a timing corner?
From PDVerse STA Mentor Guide · pdVerse Mentor Guide
Short Answer
A timing corner sets the process-voltage-temperature (PVT) condition a Liberty (.lib) library was characterized at; a SPEF corner sets the resistance and capacitance values a parasitic extraction tool computed for the same layout under a stated extraction condition. Signoff needs both because delay depends on two things that vary independently: how fast a transistor switches, and how much resistance and capacitance the surrounding wire adds. Pairing them wrong -- say, a slow-process library with a best-case, low-R low-C SPEF corner -- hides real violations instead of finding them.
Technical Explanation
A timing corner (PVT corner) selects a Liberty (LIB) library set -- process (slow/typical/fast), voltage, and temperature -- that fixes cell delay and pin capacitance for every gate in the design.
- A SPEF corner is a separate axis: it fixes the resistance-per-square and capacitance-per-unit-length the extraction tool assumed for each metal layer, independent of which Liberty library is loaded.
- Extraction tools typically publish corners named for their intent, such as a worst-capacitance corner (highest coupling capacitance, worst for setup and crosstalk push-out) and a best-capacitance corner (lowest capacitance, worst for hold and crosstalk pull-in), alongside a typical corner.
- A signoff run pairs one PVT corner with one SPEF corner per scenario; the same netlist can pass on slow-process plus typical parasitics and fail on slow-process plus worst-capacitance parasitics, because the wire-delay term changed while the cell-delay term did not.
- Setup checks usually want the pairing that maximizes total delay -- slow cells with high-R, high-C wires; hold checks usually want the opposite pairing -- fast cells with low-R, low-C wires, because that combination minimizes the useful margin between launch and capture.
- Because the two axes are independent, MCMM signoff builds its scenario matrix from every PVT corner crossed with every relevant SPEF corner, not just one representative combination.
Common Mistake
The Trap: assuming 'worst-case corner' means one single scenario, and running only the slow-PVT / worst-capacitance setup check while skipping the fast-PVT / best-capacitance hold check because 'it's the same corner list.'
- Consequence: a hold violation that only exists under low-R, low-C parasitics -- the fast, low-capacitance wires most likely on a short in-block net -- ships silently, because no scenario in the matrix ever paired fast timing with best-case SPEF.
Follow-up Question & Model Response
If both the PVT corner and the SPEF corner are already 'worst case' on their own axis, why does pairing slow-PVT with best-case parasitics ever matter for signoff coverage?
Candidate Model Response: Worst-case is check-specific, not universal -- a corner that is worst for setup is close to best for hold, so a scenario matrix that only combines worst-with-worst quietly skips the pairing that actually stresses hold. Slow-PVT cells with low-R, low-C wires shrink cell-delay variance relative to clock skew in a way a slow-plus-worst-capacitance run cannot reproduce, since the worst-capacitance corner inflates delay in the same direction as slow PVT. Signoff needs the orthogonal combination -- slow cells but light wires, or fast cells but heavy wires -- because setup and hold are stressed by opposite ends of the same two axes. Dropping that combination to save scenario count is the single most common way a real hold bug survives a clean-looking signoff report.
Practical Example
A 7nm block signs off across three PVT corners (ssg0p72v125c, ttg0p75v25c, ffg0p88vm40c) and two SPEF corners (cworst_CCworst, cbest_CCbest). The setup-critical scenario is ssg0p72v125c paired with cworst_CCworst, where slow cells and heavy coupling capacitance both push delay up. The hold-critical scenario is ffg0p88vm40c paired with cbest_CCbest, where fast cells and light capacitance both shrink delay, leaving almost no cushion for a launch flop physically close to its capture flop. Running only ssg with cworst for setup and reusing the same SPEF corner for the ffg hold check would have missed a 6 ps hold violation on a two-inverter short path that only appears once cbest_CCbest parasitics are loaded.
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