How do you decide which RC corner to use for a setup check versus a hold check?
From PDVerse STA Mentor Guide · pdVerse Mentor Guide
Short Answer
A setup check wants the parasitic corner that maximizes total delay, so it pairs with the extraction corner with the highest resistance and coupling capacitance (often labeled a worst, or RCmax, corner). A hold check wants the corner that minimizes delay and margin, so it pairs with the lowest-resistance, lowest-capacitance corner (often labeled a best, or RCmin, corner). The two checks use opposite ends of the same extraction spread because each is trying to catch the situation where timing is least forgiving for that particular check.
Technical Explanation
Extraction tools typically produce several RC corners from the same layout by varying the assumed metal width, spacing, and thickness within manufacturing tolerance, plus temperature-dependent resistivity -- not by re-routing anything.
- A worst-case (RCmax) corner assumes thinner, more resistive wires and tighter, higher-coupling spacing, which increases both net delay and crosstalk push-out -- the combination a setup check needs to find its true worst path.
- A best-case (RCmin) corner assumes thicker, less resistive wires and lower coupling, which decreases net delay and crosstalk pull-in -- the combination a hold check needs, because hold fails when a path is too fast relative to clock skew, not too slow.
- Pairing setup with RCmax and hold with RCmin is not a convention chosen for convenience -- using RCmin for a setup check would understate delay and hide a real setup violation, and using RCmax for a hold check would overstate delay and manufacture a fake hold violation that doesn't exist in real silicon.
- A signoff scenario therefore couples the analysis type -- setup or hold -- to a specific corner pairing, rather than running every check against every corner and hoping the worst number surfaces on its own.
- Some flows add a typical (RCtyp) corner purely for functional or power correlation, not for setup/hold signoff, since neither extreme is representative of typical silicon behavior.
Common Mistake
The Trap: reusing the same worst-case RC corner for both setup and hold because it is labeled worst-case in the extraction deck, without checking which direction of worst it represents.
- Consequence: running hold checks against RCmax instead of RCmin manufactures phantom hold violations that never occur in real silicon, wasting ECO effort on paths that were never actually broken, while a genuine hold risk under real RCmin conditions may go unexamined if the team assumes the RCmax run already covered 'the worst case.'
Follow-up Question & Model Response
Why doesn't a single average or nominal RC corner just serve as a safe middle ground for both checks?
Candidate Model Response: A nominal corner sits between the two extremes precisely where neither check's real worst case lives, so it under-tests both directions rather than safely covering either. Setup needs delay pushed as high as physically possible within tolerance, and a nominal corner's delay is by definition lower than that maximum, leaving margin unverified. Hold needs delay pushed as low as possible, and a nominal corner's delay is higher than that minimum, again leaving the true worst case unchecked. The two extremes are not conservative overkill -- they are the only points in the extraction spread that correspond to a check's actual failure mode, which is why signoff keeps both corners rather than collapsing to one representative value.
Practical Example
A 16nm design signs off setup against a worst-case corner at 100C, where thin, hot, tightly coupled metal-2 wires add up to 18% extra net delay versus nominal, and signs off hold against a best-case corner at minus 40C, where thick, cold, widely spaced wires cut net delay by roughly 12% versus nominal. A path from a scan-chain flop to its neighbor two cells away shows 40 ps of hold margin at the best-case corner but would show a comfortable 190 ps if mistakenly checked at the worst-case corner instead -- the wrong pairing would have hidden a real, fixable hold risk on that short local path.
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