How does total negative slack change when you turn on signal integrity analysis?

Short Answer

Turning on signal integrity (SI) analysis usually makes total negative slack (TNS) worse, because the tool now adds a delta delay for every net whose neighbors can switch at a similar time, instead of assuming clean, unaffected wires. Some paths can also improve slightly, since a neighbor switching the opposite direction can pull a signal in early instead of pushing it out.

Technical Explanation

Without SI enabled, the tool times every net using its own driver and load only, as if it were the only wire on the chip. Turning SI on changes that assumption.

• The baseline run ignores neighbors. A plain, non-SI timing run computes net delay from the driver's strength and the receiver's capacitance. It has no idea another wire runs next to it.
• SI adds a delta delay per net. With set_app_var si_enable_analysis true (PT) active and parasitics read in with read_parasitics -keep_capacitive_coupling (PT) so coupling capacitance is preserved, the tool computes an extra delay term — the delta delay — for each net based on how its neighbors are expected to switch.
• Push-out and pull-in both exist. An aggressor switching the same direction as the victim slows it down (push-out, more delay). An aggressor switching the opposite direction speeds it up (pull-in, less delay). TNS reflects the sum, so it is not automatically worse everywhere.
• In practice, TNS usually degrades. Most designs have far more paths that get pushed out than pulled in, because worst-case timing windows are built to be conservative about which neighbors could plausibly switch together.
• Why it matters: a design that looked clean without SI can show real violations once SI is enabled, and that gap is exactly what signoff is trying to catch before tape-out — not an SI bug, but a truer number.
• What breaks: comparing a pre-SI TNS number against a post-SI number as if they measure the same thing. They do not; only the SI-enabled number reflects real coupled-wire behavior.

Follow-up Question & Model Response

Would you expect a fully-routed, post-layout design to see a bigger SI-driven TNS change than an early, pre-route estimate?

Candidate Model Response: Yes, and by a wide margin. A pre-route estimate usually relies on a wire-load model or, at best, global-route parasitics, neither of which captures which specific nets run parallel to each other for a meaningful distance. Real coupling capacitance only becomes accurate once detailed routing and extraction are done, so the delta delay terms SI analysis depends on are mostly guesswork before that point. I would treat any pre-route SI number as a rough sanity check at best, and hold the real signoff decision for a run against extracted, read_parasitics-annotated data after routing is final.