What is crosstalk delay, and how is it different from crosstalk noise?
From PDVerse STA Mentor Guide · pdVerse Mentor Guide
Short Answer
Crosstalk delay is a timing effect: a neighboring wire switching at the same time pushes out or pulls in your signal's arrival time, changing when it gets there. Crosstalk noise is a voltage effect: a neighbor's switch bumps a quiet, steady wire enough that a downstream gate can briefly misread it, even though nothing on that wire was supposed to switch at all.
Technical Explanation
Both effects come from the same source — capacitive coupling between two wires that run close together for some distance — but they show up in different reports and get fixed differently.
- Same root cause, two different victims. Coupling capacitance links an aggressor net (the one switching) to a victim net (the one sitting nearby). What happens next depends on whether the victim is also switching.
- Delay happens on a switching victim. If the victim is changing state at roughly the same time as the aggressor, the coupled charge either speeds up or slows down the victim's edge — a push-out (later arrival) or a pull-in (earlier arrival), depending on whether the aggressor switches the same direction or the opposite direction.
- Noise happens on a quiet victim. If the victim is supposed to hold a steady 0 or 1, the aggressor's switch can still inject a temporary voltage bump — a glitch — even though the victim's own driver is not doing anything. This is a signal-integrity failure, not a timing-arrival failure.
- The tool reports them separately. Crosstalk delay shows up as a change to a path's arrival time in
report_timing(PT), because it affects when data gets somewhere. Crosstalk noise shows up in a dedicated static noise report, because it is about whether a logic value gets corrupted, not about being late. - Why it matters for signoff: a design can pass every setup and hold check and still fail because a noise glitch flips a state element downstream — a failure mode setup/hold analysis alone cannot see.
Common Mistake
The Trap: assuming a net that passes crosstalk delay checks is automatically safe from crosstalk noise, because both come from the same coupling capacitance.
- A designer clears the delay report and stops looking, not realizing the noise report walks a completely different condition — a quiet victim next to a switching aggressor — that the delay report never evaluates.
- The cost: a state-holding net (a flop's asynchronous reset, a static control signal) picks up a glitch large enough to flip logic, and the bug only shows up as an intermittent functional failure, not a timing report line.
Follow-up Question & Model Response
If a net never switches during normal operation, do you still need to run crosstalk noise analysis on it?
Candidate Model Response: Yes, and those rarely-switching nets need the most attention. A held-steady control or reset net has no timing path of its own, so setup and hold analysis never sees it at all. But it can still sit next to switching aggressors, and if the resulting bump is large enough relative to the receiving gate's noise-rejection margin, that gate can briefly propagate the wrong value. Static noise analysis exists specifically to catch this class of net, independent of any clock relationship.
Practical Example
A 1.2mm bus of eight data lines routes parallel to a reset line for 400 microns on metal layer M4. During one clock cycle, six of the eight data lines switch high-to-low at once while the reset line sits idle at logic 1. report_noise (PT) shows a 180mV negative bump on the reset net against a library noise-rejection threshold of 150mV — a violation, even though the reset net's own driver never moved. The fix is not a timing exception; it is adding 0.3 microns of extra spacing on that segment, cutting the coupling capacitance enough to bring the bump under 100mV.
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