IntermediateQuestion 93 of 112Source: Synopsys PrimeTime User Guide: Multiple Scenario Analysis

What information does a scenario need besides a corner, library, and clock definition?

From PDVerse STA Mentor Guide · pdVerse Mentor Guide

By Tabish Iqbal · 9+ Years VLSI Physical Design Experience

Short Answer

Beyond the PVT corner's library and the clock's SDC definition, a complete scenario also needs its own operating condition (the exact voltage and temperature point within the corner), its own set of annotated parasitics matching that corner's extraction, and its own mode-specific constraints such as case analysis settings and exceptions. Leaving any one of these tied to a different scenario's data, instead of the scenario's own, produces a result that looks complete but times the design under a mismatched, inconsistent set of assumptions.

A scenario shown as four labeled blocks that all have to align — PVT corner and library, operating condition voltage/temperature point, matching RCmax or RCmin parasitics, and mode-specific SDC — with one block highlighted red to show a mismatched, stale piece breaking the whole scenario. — Technical Reference DiagramWhat information does a scenario need besides a corner, library, and clock definition?

Technical Explanation

A scenario is often summarized as "one corner plus one mode," but that shorthand hides several pieces of data that all have to agree with each other for the scenario to mean anything.

The operating condition pins down the exact point inside the corner. A corner like "slow-slow" describes a process point, but the operating condition adds the specific voltage and temperature value the scenario is analyzed at, and that value has to match what the library and parasitics were actually characterized or extracted for.
Parasitics have to match the corner they came from. RC extraction produces different capacitance and resistance values for an RCmax corner versus an RCmin corner; a scenario built with the wrong parasitics file paired to its corner's library silently times the design under an inconsistent, physically meaningless combination.
Mode-specific SDC covers more than which clocks are active. set_case_analysis (SDC) values, timing exceptions like set_false_path (SDC) or set_multicycle_path (SDC) that only apply in one mode, and I/O delay assumptions specific to that mode all belong to the scenario's own constraint set.
Design data (netlist) is usually shared, not per-scenario, since the gates do not change between corners or modes — what changes is how fast they behave and which logic is exercised.
What breaks: assuming the corner automatically pulls in everything else. Corner, operating condition, parasitics, and mode-specific SDC are four separate pieces of data a setup script has to align deliberately.

Common Mistake

The Trap: building a new scenario by copying an existing create_scenario (PT) call and swapping only the library reference, assuming the parasitics and case analysis settings underneath still apply correctly.

A designer needs a new fast-fast-corner scenario for an existing mode, copies the slow-slow scenario's setup script, changes the library set, and reuses the same parasitics file because it "still describes the same design."
The parasitics were extracted at the RCmax corner paired with slow-slow timing, not the RCmin corner that should pair with a fast-fast scenario, so the new scenario's delay numbers reflect a corner combination that does not physically exist.

Follow-up Question & Model Response

If two scenarios share the exact same mode and only differ in PVT corner, do they need separate parasitics files?

Candidate Model Response: Usually yes, because parasitics depend on the RC extraction corner, a separate axis from the PVT timing corner even though the two are often chosen together. A setup-focused scenario typically pairs a slow timing corner with RCmax, since more R and C worsen interconnect delay, the conservative direction for setup. A hold-focused scenario pairs a fast corner with RCmin, for the same reason in reverse. So even with the mode fixed, changing the PVT corner usually means the matching parasitics corner should change too.

Practical Example

A setup-signoff scenario named func_ssg_rcmax pairs the slow-slow 0.81V/125°C library corner with RCmax parasitics, plus the functional mode's case analysis settings. A sibling hold-signoff scenario, func_ffg_rcmin, pairs the fast-fast -40°C library with RCmin parasitics and the same case analysis settings, since the mode has not changed. Building func_ffg_rcmin by copying func_ssg_rcmax's script and only swapping the library — leaving RCmax parasitics in place — would pair a fast-fast library with slow-corner interconnect data, understating hold risk.

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