What is a single flat OCV derate, and why isn't it enough for modern designs?
From PDVerse STA Mentor Guide · pdVerse Mentor Guide
Short Answer
A flat OCV derate applies the same percentage margin to every cell and every net in the design, regardless of how many logic stages a path crosses or how far apart the launch and capture clock paths are. It is simple to set up with one set_timing_derate (SDC) command, but it treats a two-stage path and a forty-stage path as equally risky, which is not how real variation behaves. As designs grow, that flat number either wastes margin on short paths or under-covers long ones.
Technical Explanation
A single number is easy to apply, but it does not match how variation actually spreads across a path.
- Random variation between transistors tends to average out over a longer chain of gates, so a path with many stages sees less net variation, in percentage terms, than a path with one or two stages.
- A flat derate ignores this averaging effect and multiplies every stage by the same factor, so it substantially over-derates long paths.
- Shrinking the flat value to stop over-flagging long paths then under-covers the short, few-stage paths where variation matters most.
- This tension is why advanced on-chip variation, AOCV, exists: it applies a smaller derate to paths with more stages and distance, and a larger derate to short, localized paths, using per-stage or per-distance lookup tables.
set_timing_derate -aocvm_guardband(SDC/PT) layers extra margin specifically for AOCV or POCV analysis, which a flat single-value derate does not use.
Common Mistake
The Trap: picking one flat derate number that "feels safe" for the whole chip and never revisiting it as the path-length mix changes.
- A number tuned during early floorplanning, when most paths were short, can quietly overprotect longer paths once pipeline depth increases.
- Teams sometimes chase schedule pressure by lowering the flat derate globally instead of switching to a stage-aware model, removing real margin from the shortest, riskiest paths too.
Follow-up Question & Model Response
If AOCV needs stage-count and distance information, where does that information come from?
Candidate Model Response: AOCV derate tables come from the technology's characterization data, supplied through the standard cell library or a vendor side file, so PrimeTime looks up a derate based on how many stages a path crosses and how far apart its launch and capture points sit on the die. Applying set_timing_derate -aocvm_guardband (SDC/PT) on top of that lookup adds margin for cases the characterization did not fully cover, such as an early floorplan where distance is still a rough estimate. As placement becomes final, that guardband is usually tightened as the distance data becomes trustworthy.
Practical Example
On a design with paths ranging from 2 to 35 stages, a flat 1.12 late derate adds 12% margin everywhere. Switching the 35-stage paths to an AOCV table that derates long, spread-out paths at roughly 1.04 instead of 1.12 recovered about 60ps of setup slack on the chip's longest register-file path, without loosening margin on the short 2-stage paths that still needed the full 1.12.
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