What is a timing mode in multi-mode multi-corner analysis?
From PDVerse STA Mentor Guide · pdVerse Mentor Guide
Short Answer
A timing mode describes one functional operating condition of the chip, such as normal function, test/scan mode, or a low-power state, each of which can activate different clocks, different enabled paths, and different constraints. The same physical chip needs to meet timing in every mode it can actually be placed into, not just the one a design team thinks of as "normal," because a path that is safely disabled in one mode might be fully active in another. Multi-mode analysis runs the design through each mode's own SDC constraints to check timing holds up in every one of them.
Technical Explanation
A mode is about which paths and constraints are active, not how fast the silicon runs.
- Different modes typically use different
set_case_analysis(SDC) settings, clock groupings, or enabled/disabled paths, since scan test and functional mode do not use the same logic the same way. - A path that is a legitimate false path in functional mode, because a control signal holds it inactive, can become a real, timed path in scan mode if that signal now toggles as part of the scan chain.
- Each mode typically has its own SDC file capturing constraints specific to that mode, so the tool needs to know explicitly which SDC applies where.
- Multi-mode analysis combines with multi-corner analysis, since each mode also needs checking across the relevant PVT and RC corners, not just one nominal condition.
- Missing a mode entirely, rather than getting its constraints wrong, is a more dangerous signoff gap, since an unanalyzed mode gives zero signal on whether its paths meet timing.
Common Mistake
The Trap: assuming functional-mode timing signoff automatically covers scan or test mode too, since it is "the same chip."
- Scan mode routes data through flip-flops in a completely different pattern, often creating new critical paths, like long scan chains, that do not exist as timing paths in functional mode.
- Skipping a dedicated scan-mode timing run is a common way a chip passes functional signoff cleanly but fails scan test at the tester.
Follow-up Question & Model Response
How many modes does a typical design actually need to define, and who decides what counts as a separate mode?
Candidate Model Response: The number of modes comes from the design's real operating states, functional, scan/test, and any distinct power or clock-gated states, decided by design and verification teams based on actual use cases, not a fixed rule. A design with several low-power states may need one mode per state if enabled paths genuinely differ, while states that never change a timing path can share one mode's constraints. Adding modes costs signoff runtime, so teams define the minimum set that produces different timing behavior.
Practical Example
A chip defines three modes, functional, scan-shift, and low-power-retention, each with its own SDC. In scan-shift mode, a control pin normally held with set_case_analysis 0 (SDC) in functional mode is left toggling for the scan chain, turning roughly 200 previously-false paths into real, timed paths only checked because the mode was analyzed separately.
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