What is set_case_analysis, and when would you tie a pin to a fixed value?
From PDVerse STA Mentor Guide · pdVerse Mentor Guide
Short Answer
set_case_analysis (SDC) tells the tool to treat a pin as permanently stuck at a fixed logic value — 0 or 1 — for the whole analysis, instead of a signal that can still switch. Designers use it for pins that really are fixed in the mode being analyzed, such as a tied-off test or configuration input.
Technical Explanation
Some pins in a real chip never actually toggle in a given operating mode, and the constraint should say so.
- What the command does:
set_case_analysis 0 [get_pins ...](SDC) orset_case_analysis 1 [get_pins ...]fixes that pin's value for the whole timing run, as if it were tied to ground or supply. - What changes because of it: any downstream logic that only matters when the fixed pin has the other value is removed from timing entirely — the tool no longer builds a path through a branch that can never be reached with that pin held constant.
- Typical real pins that get this treatment: a scan-enable pin held low during normal functional operation, or a mode-select pin on a multiplexer that is wired to one fixed value on this particular chip variant.
- It genuinely shrinks the design being timed: because whole branches of logic drop out, case analysis can also make runtime faster, not just remove irrelevant paths from the report.
- It must reflect real hardware, not a convenience: the value chosen has to match how the pin is actually wired or driven in that mode, since the tool will trust it completely and stop checking any path that assumed the other value.
Common Mistake
The Trap: applying set_case_analysis to a pin that is only fixed in one operating mode, and forgetting to re-run analysis for the other modes.
- A designer fixes a mode-select pin to run a faster, smaller timing analysis for the chip's normal functional mode, then never repeats the analysis with the pin at its other value for test mode.
- Timing for the second mode is never actually checked, and a path that only exists when the pin is at the other value ships without ever being verified.
Follow-up Question & Model Response
How is set_case_analysis different from just tying that pin to a constant in the netlist itself? Candidate Model Response: set_case_analysis (SDC) only changes what the static timing tool assumes during analysis — it does not modify the netlist or the actual silicon at all. A pin genuinely wired to ground or supply in hardware should also be described with set_case_analysis so timing reflects that reality, but the reverse is not automatic: applying the SDC command to a pin that can really still switch would hide true timing paths that silicon will actually exercise.
Practical Example
A chip's scan-enable pin, SE, is wired low during normal functional operation and high only during manufacturing test. Functional-mode timing runs with set_case_analysis 0 [get_ports SE] (SDC), which removes every scan-path timing arc from that run entirely.
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