BeginnerQuestion 72 of 95Source: Synopsys PrimeTime User Guide: Crosstalk Delay Effects

What is coupling capacitance, and why does a neighbor's switching affect your delay?

From PDVerse STA Mentor Guide · pdVerse Mentor Guide

By Tabish Iqbal · 9+ Years VLSI Physical Design Experience

Short Answer

Coupling capacitance is the capacitance that exists between two nets that run near each other on the chip, not between a net and the ground plane. Because that capacitance links the two wires electrically, a voltage change on one wire pushes some current through it onto the other, changing how quickly the second wire's own driver can charge or discharge its load. That is why a neighboring wire's switching can measurably speed up or slow down a signal's delay, an effect PrimeTime reports separately as crosstalk delay.

Two adjacent wires with a delay waveform showing pull-in (earlier edge) when they switch together and push-out (later edge) when they switch oppositely — Technical Reference DiagramWhat is coupling capacitance, and why does a neighbor's switching affect your delay?

Technical Explanation

The direction of the neighbor's switch decides whether it helps or hurts the victim's delay.

Every wire has capacitance to the ground plane and capacitance to nearby wires, called coupling capacitance; SPEF extraction reports both for every net.
If the neighbor switches in the same direction as the victim at close to the same time, the coupling adds charge in the direction the victim is already moving, pulling the transition in earlier, called crosstalk pull-in.
If the neighbor switches in the opposite direction, the coupling opposes the victim's own transition, slowing it down, called crosstalk push-out.
Coupling capacitance scales with how close two wires run and for how long they run parallel, so tighter spacing and longer parallel runs both increase this delay sensitivity.
CCS current-source models let PrimeTime SI calculate this coupled delay change more accurately than a simpler delay model, since they represent the driver's real current-voltage behavior instead of a fixed resistance.

Common Mistake

The Trap: assuming crosstalk delay always makes a path slower, since "crosstalk" sounds like it should only hurt.

Push-out slows a path down, but pull-in speeds it up, and a design that only checks for slow-down can miss a pull-in that turns a marginal hold path into an actual violation.
Signoff needs both directions checked, since the same coupling mechanism can be either a setup risk or a hold risk depending on how the neighboring switch happens to line up.

Follow-up Question & Model Response

If wider wire spacing always reduces coupling capacitance, why doesn't every design just route everything with maximum spacing?

Candidate Model Response: Wider spacing does reduce coupling, but routing resources are limited, and spreading every wire out to minimize coupling would use far more tracks than most dense blocks have available, especially near the clock tree or memory interfaces. Design teams typically reserve wider spacing or shielding for the specific nets SI analysis flags as high-risk, such as long buses running parallel to a clock, and accept tighter routing everywhere coupling risk is low. This targeted approach gets most of the benefit without paying the full routing-density cost across the whole chip.

Practical Example

Two 1.5mm data wires routed with minimum spacing show 40fF of coupling capacitance between them, versus only 12fF at double the spacing. When they switch in opposite directions near the same time, the minimum-spacing pair sees a 35ps delay push-out on the victim, while the wider-spaced pair sees only about 10ps, enough to keep it inside its setup margin.

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