Why does STA need annotated parasitics instead of just a wire load model?
From PDVerse STA Mentor Guide · pdVerse Mentor Guide
Short Answer
A wire load model estimates a wire's resistance and capacitance from statistics, an average length for a given fanout, before the design has real placement or routing. Annotated parasitics come from actually extracting the resistance and capacitance of the wires the tool physically routed, captured in a SPEF file, so they reflect the real length, shape, and neighbors of every specific wire. Once real layout exists, using annotated parasitics instead of a statistical estimate is what lets STA correlate with how the chip will actually behave.
Technical Explanation
A statistical average and a real, routed wire rarely agree once layout exists.
- A wire load model is a table that estimates capacitance and resistance from a net's fanout count and the design's total size, since no individual wire has been drawn yet at that stage.
- Two nets with the same fanout can end up with very different actual lengths after placement and routing, so one average estimate is often wrong for any specific net.
- Annotated parasitics come from back-annotating a SPEF file, generated by the extraction tool from the actual routed geometry, so each net's RC reflects its real, specific route.
- Annotated parasitics also enable SI analysis, since crosstalk depends on which specific nets are actually adjacent in real layout, information a wire load model does not contain.
- Early in the flow, before placement, a wire load model is the only option available; the goal is to move to SPEF-based parasitics as soon as real routing exists.
Common Mistake
The Trap: continuing to sign off timing with a wire load model on a design that already has real, routed geometry available.
- Wire load model estimates can be significantly optimistic or pessimistic for a specific net, especially very long or very short nets far from the fanout table's average.
- Signing off on wire load model numbers after routing risks a chip that reports clean timing in the estimate but has real violations once annotated parasitics are checked.
Follow-up Question & Model Response
If annotated parasitics are always more accurate, why does the flow ever use a wire load model at all?
Candidate Model Response: Early in synthesis, no real wires exist yet to extract, so there is nothing to annotate, and the design still needs some interconnect estimate to make sensible decisions about cell sizing and buffering. A wire load model gives synthesis a reasonable, if approximate, starting assumption instead of treating every net as zero-delay, which would produce an unbuildable netlist. As placement then routing produce real geometry, the flow switches to progressively more accurate interconnect estimates, ending in full SPEF-based annotated parasitics.
Practical Example
A net with a fanout of 4 gets a wire load model estimate of 150fF regardless of where its driver and four loads actually land. After routing, that net's real SPEF-annotated capacitance turns out to be only 60fF because placement kept the driver and loads close together, which changes the reported delay on that arc by nearly half.
Complete STA Handbook
Master Signoff-Ready Static Timing Analysis
Get the complete 10-chapter STA handbook covering setup/hold margins, clock modeling, OCV/POCV, crosstalk noise, and PrimeTime closure.
Continue practising