BeginnerQuestion 60 of 95Source: Synopsys PrimeTime User Guide: Timing Paths and Exceptions

What is set_max_delay and set_min_delay, and how do they differ from set_false_path?

From PDVerse STA Mentor Guide · pdVerse Mentor Guide

By Tabish Iqbal · 9+ Years VLSI Physical Design Experience

Short Answer

set_max_delay and set_min_delay (SDC) give a path an explicit time budget in nanoseconds directly, instead of deriving one from a clock relationship. set_false_path (SDC) removes a path from checking entirely; these two commands keep the path checked, just against a number the designer states outright.

A path between two registers labelled with an explicit 12 nanosecond max-delay value instead of a clock-derived required time — Technical Reference DiagramWhat is set_max_delay and set_min_delay, and how do they differ from set_false_path?

Technical Explanation

Sometimes a path's real timing requirement does not come from any clock relationship at all.

What the commands actually set: set_max_delay 12 -from REGA -to REGB (SDC) tells the tool the path must arrive within 12ns, full stop — no clock period is involved in computing that number.
set_min_delay is the hold-side equivalent: it states an explicit lower bound on how fast the path may arrive, serving the same role a hold check would, but again stated directly instead of derived from clock edges.
When this is the right tool: a path with no natural launch/capture clock relationship — for example, one governed only by an external protocol's timing spec — still needs a real requirement, and a stated max/min delay gives it one.
Why this is not the same as removing the path: set_false_path (SDC) says "do not check this at all"; set_max_delay/set_min_delay say "check this, but against this specific number instead of the clock-derived one."
They can also override a clock-derived requirement: applying set_max_delay to a path that does have a clock relationship replaces the clock-derived required time with the stated one, which is sometimes used to deliberately tighten or loosen one specific path.

Common Mistake

The Trap: reaching for set_false_path (SDC) on a path that actually needs a real, just-not-clock-derived, timing requirement.

A designer wants to stop a path from showing up as a clock-based violation and marks it a false path, when the path genuinely does need to meet some real-world timing budget.
The path is now checked against nothing at all, and a genuine timing failure on it — one that would have shown up against an explicit set_max_delay number — is never caught.

Follow-up Question & Model Response

If a path already has a clock-derived setup requirement, why would you override it with set_max_delay instead of just adjusting the clock period? Candidate Model Response: Changing the clock period affects every path in that domain, not just the one you care about, so it is a blunt tool for a single path's problem. set_max_delay (SDC) applied with -from/-to targets exactly one path, letting the designer state a tighter or looser requirement for that specific connection alone, without disturbing every other register in the same clock domain.

Practical Example

A path from register REGA to register REGB must complete within 12ns per a system-level protocol spec, independent of either register's own clock period. The SDC file states set_max_delay -from [get_cells REGA] -to [get_cells REGB] 12 directly.

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