BeginnerQuestion 57 of 95Source: Synopsys PrimeTime User Guide: Timing Paths and Exceptions

Why would a designer mark a path as a false path instead of just leaving it unconstrained?

From PDVerse STA Mentor Guide · pdVerse Mentor Guide

By Tabish Iqbal · 9+ Years VLSI Physical Design Experience

Short Answer

Leaving a path unconstrained means the tool never checks it at all and cannot tell an intentionally irrelevant path from a genuine constraint gap. Marking it a false path with set_false_path (SDC) is a deliberate, documented statement that the path was checked and judged not to need timing at all.

Two identical reset-only paths side by side, one labelled unconstrained with a question mark and one labelled false path with a documented reason — Technical Reference DiagramWhy would a designer mark a path as a false path instead of just leaving it unconstrained?

Technical Explanation

The two situations look similar in a report but mean very different things.

What an unconstrained path signals: it means the tool has no startpoint/endpoint clock relationship or I/O delay to build a check from — a missing constraint, which check_timing (PT) flags as something to fix.
What a false path signals: the path is fully constrained and could be checked, but the designer has decided, for a specific, understood reason, that its actual delay does not matter functionally.
A typical real reason for a false path: a path only ever carries a value during chip reset or configuration, well before the clock is running at full speed, so its worst-case combinational delay is functionally irrelevant.
set_false_path is documentation as much as a command: a reviewer looking at report_timing (PT) or the SDC file sees the exact path excluded and, ideally, why, rather than wondering whether a constraint was simply forgotten.
The cost of leaving it unconstrained instead: check_timing (PT) keeps flagging it as a missing constraint every single run, and nobody reviewing the SDC file can tell whether that gap is intentional or a bug waiting to be found.

Common Mistake

The Trap: treating "the path doesn't matter" and "the path is unconstrained" as interchangeable, and just never adding a constraint at all.

A designer decides a reset-only path is irrelevant and simply never writes a set_input_delay/set_output_delay (SDC) for it, rather than constraining it properly and then excluding it with set_false_path.
The next engineer to run check_timing (PT) sees an unconstrained endpoint warning with no explanation, cannot tell if it is safe, and has to re-investigate a decision that was already made once.

Follow-up Question & Model Response

Does marking a path false path mean the tool ignores it completely, forever? Candidate Model Response: Within setup and hold analysis, yes — set_false_path (SDC) removes that specific path from every future setup and hold check, and it stays excluded until the constraint is edited or removed. It does not, however, remove the path from design rule checks like max transition or max capacitance, since those checks look at one signal's electrical properties, not the clock relationship the false path exception is about.

Practical Example

A configuration register's output only ever changes while RESET_N is held low, well before the core clock is enabled. The path is fully constrained through the normal clock, then excluded with set_false_path -from [get_pins cfg_reg/Q] -to [get_pins core_logic/D] (SDC), with a comment noting it is reset-only.

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