What is set_disable_timing, and when would you turn off an entire timing arc?

Short Answer

set_disable_timing (SDC) removes one specific timing arc — a delay from one pin to another inside a cell or between two points — from analysis entirely, as if that internal connection did not exist. It is used when a real electrical path exists but is never functionally active in the mode being timed.

Technical Explanation

Some connections inside a cell or design are electrically present but never carry a meaningful signal in the mode being analyzed.

• What an arc is, in this context: a single input-pin-to-output-pin delay relationship inside a cell, such as one specific path through a multiplexer or a scan-enabled flip-flop cell.
• What the command actually removes: set_disable_timing [get_cells ...] or a pin-to-pin form (SDC) removes that one arc from the timing graph, so no path is ever built through it, in either direction.
• A common real use case: a scan-capable flip-flop cell has an internal arc from its scan-input pin to its output, which is only functionally meaningful during scan test, not during normal operation — disabling it keeps functional-mode analysis focused on the real data path.
• Different from a false path in scope: set_false_path (SDC) excludes one specific path defined by its startpoint and endpoint; set_disable_timing removes an arc everywhere it appears, which can affect every path that happens to route through that internal connection.
• Why it must be used carefully: because the effect is structural, disabling the wrong arc can silently remove a real, still-active functional path from every report, not just the one the designer intended to exclude.

Follow-up Question & Model Response

How is set_disable_timing different from set_case_analysis for a scan-enable pin? Candidate Model Response: set_case_analysis (SDC) fixes a pin's logic value and lets the tool figure out, from that fixed value, which downstream branches become unreachable on its own. set_disable_timing (SDC) is more direct — it names the exact arc to remove regardless of any pin value, which is useful when the unwanted arc is internal to a library cell and not simply the consequence of a pin being held constant. The two are complementary: case analysis handles reachability through logic, disable timing handles a specific known-inactive internal connection.