IntermediateQuestion 107 of 112Source: Synopsys PrimeTime User Guide: Timing Signoff Checklist

What timing checks must be clean before a design can tape out?

From PDVerse STA Mentor Guide · pdVerse Mentor Guide

By Tabish Iqbal · 9+ Years VLSI Physical Design Experience

Short Answer

Tapeout signoff is not one number, it is a checklist that every setup and hold check passes across every signoff corner and mode, every design-rule check like max transition and max capacitance is clean, and every endpoint in the design is actually constrained. Missing any one item on that list, even while the main slack number looks clean, means the design is not ready to tape out.

Signoff checklist diagram with four gates: 64/64 MCMM scenarios clean, zero unconstrained endpoints, all 40 exceptions matching real paths, and DRC checks clean, all required before a tapeout release stamp. — Technical Reference DiagramWhat timing checks must be clean before a design can tape out?

Technical Explanation

Setup and hold checks must be clean, no negative slack, across every scenario in the signoff matrix, not just the nominal or typical corner used during early development.
MCMM coverage must be complete: every mode-corner combination the chip will actually see in the field needs its own scenario run and reviewed separately, since a clean typical corner says nothing about a clean worst-case one.
Design rule checks such as max transition and max capacitance, reported through report_constraint -max_transition and report_constraint -max_capacitance (PT) against library-derived limits, must also be clean, these catch signal-integrity and reliability risks a pure setup/hold slack number does not capture.
No endpoint may be left unconstrained, check_timing (PT) flags missing input or output delays, and an unconstrained endpoint is simply never checked at all, which can hide a real violation behind a report that looks clean.
Any exceptions applied with set_false_path or set_multicycle_path (SDC) need to be confirmed as intentional and still matching real paths, since an exception hiding a genuine violation is worse than no exception at all.
ECO changes made late in the flow must be re-verified with a fresh, full timing run rather than trusted from the pre-ECO report, since a physical change can shift derates, parasitics, or even which path is worst.

Common Mistake

The Trap: Treating a clean setup/hold report at the nominal corner as proof the design is signoff-ready.

Real chips ship across a range of voltage, temperature, and process variation, so a corner that was never run, or an endpoint that was never constrained, can hide a violation that only appears in the field.

Follow-up Question & Model Response

If every individual checklist item passes, is there anything else that could still block tapeout from a timing standpoint?

Candidate Model Response: Yes, the checklist confirms static timing is clean, but it assumes the constraints themselves are correct, and a wrong or missing constraint can make a genuinely broken path look perfectly fine. Teams also review whether every clock relationship, case-analysis mode, and asynchronous crossing was actually modeled, since a static timing report can only be as trustworthy as the SDC that drives it. A functional or clock-domain-crossing review, done separately from STA, is what catches the class of bug a clean timing report cannot see by design. This is also why the ECO and timing signoff process in physical design cross-checks these same items from the implementation side before final tapeout approval.

Practical Example

A 7nm SoC signoff matrix has 64 MCMM scenarios; before tapeout the team confirms all 64 show zero setup and hold violations, check_timing (PT) reports zero unconstrained endpoints across all of them, and every one of the design's 40 set_false_path (SDC) exceptions still matches at least one real path under report_exceptions (PT). Only after all three conditions hold together does the design move to tapeout release.

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