What are max_capacitance limits, and is max_fanout also covered by these library references?
From PDVerse STA Mentor Guide · pdVerse Mentor Guide
Explanation
max_capacitance is a design-rule ceiling in the standard cell library specifying the largest output load (capacitance) a cell or pin is allowed to drive, listed as a pin-group attribute in the liberty data alongside max_transition. Like max_transition, exceeding it is a DRC failure regardless of the path's slack.
Timing-path Walkthrough
These limits exist to keep a cell operating within the range the library was characterized for; driving beyond max_capacitance risks the same kind of extrapolated, unreliable delay numbers that an out-of-range transition would cause. The notes list max_capacitance and max_transition together as liberty pin-group attributes representing these design-rule ceilings.
Expected Report Behavior
A max_capacitance violation appears as a DRC failure on the driving pin in design-rule reporting, separate from slack-based setup/hold reports.
Mentor Note — Common Mistake
Not sufficiently covered in the supplied reference documents regarding max_fanout specifically — the notes do not mention max_fanout at all, so no details about it (whether it is or isn't covered by the same liberty references) can be stated without fabrication.
How To Debug
Check the liberty pin-group attributes (max_capacitance, max_transition) against actual loads/slews on each pin as part of DRC verification, before trusting slack-based reports on the same paths.
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