Why can a design pass timing at the typical corner and still fail signoff at a corner you didn't check?
From PDVerse STA Mentor Guide · pdVerse Mentor Guide
Short Answer
A single corner combines one process, one voltage, and one temperature assumption, and different corners can make different checks the worst one, a fast, low-voltage corner tends to be worst for hold while a slow, high-voltage corner tends to be worst for setup. A design that only reports clean at the typical corner has simply never been checked against the corner where its real worst violation would show up.
Technical Explanation
- Process, voltage, and temperature (PVT) each shift cell and interconnect delay, sometimes in opposite directions for the same path depending on which corner combination is applied.
- A fast-process, high-voltage, low-temperature corner tends to minimize delay, exactly the condition where hold violations are most likely to appear, since data races ahead of the clock.
- A slow-process, low-voltage, high-temperature corner tends to maximize delay, where setup violations are most likely, since data struggles to arrive before the next clock edge.
- Signoff practice runs a matrix of scenarios, each a specific mode and corner combination, precisely because no single corner is guaranteed to expose every kind of violation the chip could see across its real operating range.
- A design that only ever ran the typical corner during early development can look completely clean, simply because it was never asked the question a worse corner would have raised.
- This is different from a scenario simply being missing from the matrix by oversight, the design here may have a properly defined matrix, but a designer reviewing a single "looks clean" report without checking which corner it came from can still draw the wrong conclusion.
Common Mistake
The Trap: Seeing one clean timing report in a review meeting and assuming the design is signoff-ready, without checking which corner and mode that specific report was generated from.
- The same design can have a genuinely violating path at a corner nobody in the room happened to be looking at, and the meeting's confidence is based on an incomplete picture.
Follow-up Question & Model Response
If temperature inversion means a hot corner is not always the slowest one, how does that complicate picking the worst-case corner for setup?
Candidate Model Response: In some advanced process nodes, cell delay actually decreases as temperature rises at low voltage, the opposite of the older assumption that hot always means slow, a behavior called temperature inversion. This means the traditionally assumed worst-case setup corner, high temperature and low voltage, may not actually be the slowest combination for every cell in every library at every node. Signoff teams handle this by running the full PVT matrix rather than guessing which corner is worst ahead of time, since guessing wrong based on an outdated assumption would leave the real worst corner unchecked. This is one reason the signoff matrix keeps growing rather than shrinking as process nodes get more advanced.
Practical Example
A design reviewed only at the typical corner, nominal voltage, 25 degrees Celsius, typical process, shows every path with more than 100ps of setup slack. Once the full 24-corner signoff matrix is run, the slow-process, low-voltage, 125 degree corner shows the same clock domain at -45ps on three paths that were never close to failing at the typical corner, forcing an ECO the review meeting had no reason to expect.
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