ExpertQuestion 41 of 69Source: Synopsys PrimeTime User Guide: Clock Reconvergence Pessimism Removal

Why can clock uncertainty, OCV derating, and CRPR all apply to the same path at once, and how does that stack into a hidden pessimism budget?

From PDVerse STA Mentor Guide · pdVerse Mentor Guide

By Tabish Iqbal · 9+ Years VLSI Physical Design Experience

Short Answer

A single path can carry clock uncertainty margin, an OCV derate percentage, and a CRPR credit all at the same time, because each one models a different source of variation and the tool applies them independently. Stacked together they can consume far more margin than any one term suggests, which is why a path that looks comfortably positive on a naive hand calculation can still fail in the signoff report. Reading a slack number without knowing which margins are baked into it is the real risk, not any single margin being "too conservative."

Stacked bar showing clock uncertainty, OCV derate, and CRPR credit combining on a single setup path, with two paths at equal 35ps slack but different real margin (8ps vs 85ps) — Technical Reference DiagramWhy can clock uncertainty, OCV derating, and CRPR all apply to the same path at once, and how does that stack into a hidden pessimism budget?

Technical Explanation

Clock uncertainty (set_clock_uncertainty (SDC)) is a flat number subtracted from the required time to cover jitter and any residual skew the tool cannot compute directly.
OCV/AOCV/POCV derating (set_timing_derate (PT)) scales every cell and net delay on the path by a percentage or a per-arc sigma, modeling die-to-die and within-die process, voltage, and temperature spread.
CRPR (clock reconvergence pessimism removal) then gives back some of that derate on the common portion of the clock tree that the launch and capture paths share — never on the whole path.
These three mechanisms are computed independently, in that order, on every path the tool times — none of them knows what the other two contributed.
Because they attack different physical effects, the tool has no reason to cap their combined effect; three honest, narrow margins can still add up to a large one.
A path with many stages of common clock and only a short divergent tail gets almost all its derate reversed by CRPR; a path with a short common trunk and a long divergent tail keeps nearly the full derate on both sides.
The result: two paths with identical nominal slack can carry very different effective margin once uncertainty, derate, and CRPR are all applied, and neither number is printed as a separate line by default.
What breaks: an engineer who "closes" a path to a small positive number without checking how much of that number is margin, not real logic delay headroom.

Common Mistake

The Trap: Treating the printed slack as if it were one clean, comparable number across paths, without asking how much clock uncertainty, derate, and CRPR each contributed to it.

Two paths with the same reported slack can have very different real risk if one path's clock tree shares almost nothing between launch and capture, so CRPR gave it almost no credit back.
Engineers who fix the "worst" path by nominal slack alone can spend an ECO cycle on a path that already has generous hidden margin, while a path with less margin waits.

Follow-up Question & Model Response

"If I report_timing on the two paths and see the same slack, how do I actually tell which one is riding on more margin?"

Candidate Model Response: Use report_timing (PT) with full path detail so the report prints the clock uncertainty line, the derate factor applied to each arc, and the CRPR credit as a separate line item, not folded silently into the arrival and required times. Comparing those three numbers between the two paths shows which one has a bigger derate-minus-CRPR gap, meaning it is carrying more real margin for the same reported slack. A path with a small gap is closer to its true, un-derated timing and deserves the fix priority even if its nominal slack looks the same. This is also why signoff reviews should never rank paths by slack alone once OCV and CRPR are both active.

Practical Example

Consider two reg-to-reg paths in a 1.2 GHz core, both reporting 35 ps of setup slack at the SSG 0.72V 125°C corner. Path A shares 18 clock-tree stages between launch and capture flops with only 2 stages of divergence; CRPR removes 92 ps of the 100 ps derate applied to those shared stages, leaving 8 ps of real margin. Path B shares only 3 stages, so CRPR removes just 15 ps of a comparable 100 ps derate, leaving 85 ps of real margin. Both report 35 ps slack, but path A is one silicon corner away from failing while path B has genuine headroom — a fact invisible until the CRPR and derate lines are read individually.

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