BeginnerQuestion 45 of 95Source: Synopsys PrimeTime User Guide: Reporting Timing Paths

Why can multiple paths end at the same flip-flop, and which one does STA report?

From PDVerse STA Mentor Guide · pdVerse Mentor Guide

By Tabish Iqbal · 9+ Years VLSI Physical Design Experience

Short Answer

A flip-flop's data input is usually fed by several different upstream logic paths that converge through a mux or a gate, so more than one path can share the same endpoint. The tool reports the one with the worst slack for that endpoint, not every path that reaches it.

A 2-to-1 mux feeding one flip-flop's data pin from two upstream paths of different lengths, with the worst-slack path marked as the reported one — Technical Reference DiagramWhy can multiple paths end at the same flip-flop, and which one does STA report?

Technical Explanation

An endpoint is a pin, not a single wire, so several paths can arrive there.

Why convergence happens: a data input on a flip-flop is often the output of a multiplexer selecting between two or more sources, or an AND/OR gate combining several signals — every one of those upstream paths ends at the same pin.
The tool checks each one: internally, the tool computes arrival time and slack for every distinct path reaching that endpoint under the active mode, not just one.
What a default report shows: report_timing (PT) without extra options shows only the single worst path per endpoint by default, because that is the one that determines whether the endpoint passes or fails.
Other paths are not deleted, just not printed: a second path reaching the same flip-flop with better slack is still checked internally — it is simply not the worst one, so it does not appear unless the designer asks for more paths.
How to see the rest: the -nworst option on report_timing (PT) prints the N worst paths per endpoint, which is how a designer confirms whether a second, nearly-as-bad path is hiding behind the one shown.

Common Mistake

The Trap: fixing the one path a default report_timing (PT) shows and assuming the endpoint is done.

A designer buffers or resizes cells along the single worst path shown, then reruns the report and sees the number improve, and stops there.
A second path into the same flip-flop, close behind the first in slack, becomes the new worst path and was never looked at, so the endpoint can still fail after the fix.

Follow-up Question & Model Response

If two paths reach the same flip-flop, do they share the same required time? Candidate Model Response: Yes — the required time at an endpoint comes from the capturing clock edge and any exceptions on that endpoint, and it does not depend on which upstream path is arriving. So every path converging on that flip-flop is judged against the same deadline; only their arrival times differ, based on the logic and wire delay each one accumulated on its own route to the pin.

Practical Example

Flip-flop FF9's data input is a 2-to-1 mux selecting between a fast bypass path (arrival 1.2ns) and a slower ALU-result path (arrival 2.6ns), both under a 3ns required time. report_timing (PT) reports only the ALU path by default, with 0.4ns slack; running with -nworst 2 also shows the bypass path at 1.8ns slack.

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