BeginnerQuestion 46 of 95Source: Synopsys PrimeTime User Guide: Specifying Clocks

What is a virtual clock, and why would you create one that doesn't drive any pin?

From PDVerse STA Mentor Guide · pdVerse Mentor Guide

By Tabish Iqbal · 9+ Years VLSI Physical Design Experience

Short Answer

A virtual clock is a clock the designer defines with create_clock (SDC) but never attaches to any real port or pin in the design. It exists only so the tool has a timing reference for signals that talk to an off-chip device on a clock the chip itself does not generate.

A chip output port with set_output_delay referencing a virtual clock box drawn with a dashed outline to show it has no physical source pin — Technical Reference DiagramWhat is a virtual clock, and why would you create one that doesn't drive any pin?

Technical Explanation

Every I/O delay needs a clock to be relative to, even when that clock is not really inside the chip.

Why a normal clock will not do: set_input_delay and set_output_delay (SDC) both require a -clock argument, and that clock must already exist somewhere in the design before you can reference it.
What makes a clock virtual: you call create_clock (SDC) with a name but no get_ports/get_pins argument, so the clock has a period and a waveform, but no real source anywhere in the netlist.
Where it is used: a chip talking to an external memory or another chip over a shared bus often needs its I/O timed against the sender's clock edge, which physically lives off-chip and was never brought onto this design's clock tree.
It never gets skew or latency from real hardware: because nothing in the design drives it, a virtual clock has no clock tree, so any latency it needs must be typed in by hand with set_clock_latency (SDC).
It behaves like any other clock for I/O timing: once created, set_input_delay -clock vclk (SDC) and set_output_delay -clock vclk (SDC) work exactly the same as they would against a real, physical clock.

Common Mistake

The Trap: assuming a virtual clock must be missing from the design because report_clock_timing (PT) shows no propagation for it.

A designer sees no clock tree data for the virtual clock and assumes the SDC file has an error, when the missing tree is expected — the clock was never meant to have one.
Trying to "fix" it by attaching the virtual clock to a real pin breaks the intent, since that pin then gets treated as an actual clock source it was never meant to be.

Follow-up Question & Model Response

If a virtual clock has no source pin, how does the tool know its edges even exist? Candidate Model Response: The tool takes the period and waveform values given to create_clock (SDC) at face value — it does not need a physical source to compute edge times, only the numbers the designer supplies. Those edges are then used purely as a reference for comparing against I/O delay values on real ports. The virtual clock never appears anywhere else in the design, so it never contributes to internal setup or hold checks, only to the I/O interface it was created for.

Practical Example

A chip's output bus is captured by an external ASIC on a 200MHz clock the external device generates. The designer writes create_clock -name vclk -period 5 with no port argument, then set_output_delay 1.2 -clock vclk [get_ports DATA_OUT*] to constrain the interface against that off-chip edge.

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