Why can't a single corner catch every timing problem in a modern chip?
From PDVerse STA Mentor Guide · pdVerse Mentor Guide
Short Answer
Different timing checks are stressed by opposite physical conditions: setup checks get worse when the silicon runs slow, and hold checks get worse when it runs fast, so no single PVT corner is the worst case for both at once. A chip also has to work across its full specified range of voltage, temperature, and manufacturing outcome, not just one assumed condition, so checking only one corner leaves the rest of that range completely unverified. This is why signoff always runs multiple corners rather than trying to find one corner that represents every risk.
Technical Explanation
The physical conditions that hurt setup and hold point in opposite directions.
- Setup checks fail when data arrives too late, which gets worse as delays increase, so the slow-process, low-voltage, high-temperature corner is typically the hardest setup corner.
- Hold checks fail when data arrives too early, which gets worse as delays decrease, so the fast-process, high-voltage, low-temperature corner is typically the hardest hold corner.
- A single "typical" corner, between these extremes, stresses neither check as hard as its own dedicated extreme corner, so relying on typical alone under-covers both.
- Beyond setup and hold, checks like maximum transition or maximum capacitance can be worst at yet another corner combination, since slew degradation depends on drive strength and load in ways that do not always track setup or hold.
- Because manufactured chips genuinely land anywhere within the process's specified range, and operate anywhere within their voltage and temperature range, signoff has to demonstrate correct timing across that whole range.
Common Mistake
The Trap: picking the corner that is "worst" by general intuition, like highest temperature alone, and assuming it covers every check.
- High temperature alone does not automatically mean worst-case for every combination of process and voltage.
- A team that signs off using only one intuitively conservative-sounding corner risks missing violations that only appear at the true opposite-extreme corner for a different check type.
Follow-up Question & Model Response
Given that more corners means more signoff runtime, how do teams decide the minimum corner set that still gives real confidence?
Candidate Model Response: Teams typically start from the corners the library vendor documents as intended signoff corners, since those represent the process's specified extremes, then add any corners the design's own operating specification requires, such as a wider temperature range for an automotive part. Some teams also run a broader corner sweep once, early on, to confirm the smaller regular set actually captures the true worst case for setup, hold, and DRC checks, and only trust the smaller set once that check passes. This turns an assumption into a validated one.
Practical Example
A 1.6GHz DDR interface is specified for 0.72V to 0.88V across -40C to 150C, over SS and FF corners. The nominal 0.8V, 25C corner alone reports 50ps of worst setup slack. The SS corner at 0.72V/150C drops that path to -18ps, a violation the nominal check never showed, while the FF corner at 0.88V/-40C separately reports a -6ps hold violation on a different path.
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