IntermediateQuestion 78 of 112Source: Synopsys PrimeTime User Guide: Operating Conditions

Why do you still need on-chip variation margin even after running timing at every PVT corner?

From PDVerse STA Mentor Guide · pdVerse Mentor Guide

By Tabish Iqbal · 9+ Years VLSI Physical Design Experience

Short Answer

A PVT corner models variation between chips or across a whole die — one chip running slightly hot and slow, another cool and fast — using one fixed set of conditions for the entire design in that run. On-chip variation (OCV) margin instead models variation between two points inside the very same chip in the very same run, which a corner, by definition, holds constant.

One chip die shown twice: once at a uniform SSG corner condition applied everywhere, and once zoomed into two nearby flip-flops on that same die showing a small local OCV-derate gap between them that the corner alone doesn't model. — Technical Reference DiagramWhy do you still need on-chip variation margin even after running timing at every PVT corner?

Technical Explanation

PVT corners and on-chip variation margin answer two different questions about where variation comes from, and a design needs both.

A PVT corner fixes process, voltage, and temperature for the whole chip in one run. A slow corner (say, SSG at low voltage and high temperature) assumes every transistor on the chip is uniformly slow for that analysis, which models chip-to-chip and die-to-die spread.
Real variation also happens within a single chip. Even on one die held at one nominal voltage and temperature, transistors a few millimeters apart can differ slightly due to local manufacturing variation, and voltage can sag differently in different regions under switching activity.
A corner run alone cannot see that local difference. Since the whole chip is analyzed at one fixed process/voltage/temperature point per corner, two flip-flops in the same corner run are assumed to have identically-behaving surrounding logic, which is not exactly true in silicon.
OCV margin adds exactly that missing local spread. set_timing_derate (SDC) or AOCV/POCV derating adds margin for the difference between two nearby points on the same chip, layered on top of whatever corner is already being analyzed.
Skipping OCV margin because "the design already runs multiple corners" misses the point. Corners and OCV margin cover different, additive sources of variation — one between chips, one within a chip — and dropping either one leaves a real gap in coverage.
Signoff typically runs OCV-derated analysis at each relevant corner, not one or the other, precisely because both effects are real and neither one substitutes for the other.

Common Mistake

The Trap: believing that running timing at a slow corner and a fast corner already covers all the margin a design needs, making OCV derating redundant.

A designer sees the design already signs off at SSG and FFG corners and questions why an additional derate factor is needed on top.
Corners model chip-to-chip spread, not the local, within-die spread between two nearby points that OCV margin specifically covers — dropping OCV margin leaves that within-chip risk completely unchecked, no matter how many corners are run.

Follow-up Question & Model Response

A teammate proposes dropping OCV derating to speed up signoff, arguing the SSG and FFG corner runs already cover worst-case and best-case behavior. How do you respond?

Candidate Model Response: Corners and OCV margin cover different sources of variation, so dropping one does not make the other redundant. SSG and FFG model a whole chip being uniformly slow or fast, capturing chip-to-chip spread, but within any single corner run the tool still assumes every gate behaves identically. Real silicon has local differences between two points on the same die, and OCV derating protects against exactly that gap. I would keep it active at each corner rather than treating corners as a substitute, since removing it leaves a real, uncovered risk regardless of how many corners run.

Practical Example

A design signs off at an SSG corner (0.72V, 125°C) and an FFG corner (0.88V, -40°C), both with on-chip variation derating active via set_timing_derate -early/-late (SDC) layered on top of each corner. Removing OCV derating from the SSG corner run alone recovers about 60ps of apparent slack on a critical path, but that recovered margin exists only in the report — the real chip still has local process and IR-drop differences between the path's two flip-flops that the corner alone never modeled, regardless of which single PVT point the corner fixes for the whole die.

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