How does placement respect voltage areas, and what goes wrong at the boundaries?
From PDVerse Low-Power Physical Design Mentor Guide · pdVerse Mentor Guide
Short Answer
The placer treats each voltage area as an exclusive move bound: a domain's cells must go inside its voltage area, and every other cell must stay out. Isolation and level shifter cells follow their strategy location, so they collect along voltage-area edges, and dual-rail cells also need to sit near their secondary straps. Most boundary problems come from crowding at those edges, guard bands that eat space, and cells that end up in the wrong area after an ECO.
Technical Explanation
- Exclusive move bound: cells of PD_COP are legal only inside the PD_COP voltage area; all others are kept out.
- Strategy location: a self location puts isolation or level shifters inside the domain, parent puts them in the parent, so edges fill up.
- Guard bands add keepout rings, so the usable area near edges is smaller than the floorplan outline suggests.
- Dual-rail cells also obey secondary PG placement constraints, which can pull them toward straps and away from their logic.
- Edge crowding raises local density, creating congestion and long detours for the crossing nets.
- After ECOs, moved or new cells can land in the wrong voltage area;
legalize_placement(ICC2) finalizes locations andcheck_mv_design(ICC2) flags domain mismatches. - A cell placed in the voltage area of a different domain gets the wrong rail, which is a functional failure, not just a timing one.
Common Mistake
The Trap: Sizing a voltage area only for its logic cells and forgetting the isolation and level shifter cells that must also sit at its edge.
- The edge rows overflow, the legalizer pushes cells deep into the area, and crossing nets detour to reach them.
- Timing on boundary paths gets worse and the level shifter delay budget is blown before routing even starts. Widening the voltage area at that point means a new floorplan iteration.
Follow-up Question & Model Response
"What checks do you run after placement in an MV design?"
Candidate Model Response: Start with a full check_mv_design (ICC2) run to confirm no cell sits in the wrong domain and no strategy lost its cells. Then run check_legality (ICC2) for placement-rule and secondary PG constraint violations. Look at a density map around each voltage-area edge for crowding. Finally, trace a couple of crossing nets with report_mv_path (ICC2) to confirm isolation and level shifters sit where the strategy says. Fix edge crowding now, because after CTS every moved cell also moves clock and timing.
Practical Example
Design Scenario: (illustrative) PD_COP has 180 output ports isolated at location self, plus 40 low-to-high level shifters on its inputs. That is about 1,100 um² of MV cells, all wanting the first few rows inside the PD_COP edge. The floorplan gave PD_COP 65% overall utilization, but the edge rows reach 95%, and 12 isolation cells get pushed 30 um inward. The team widens PD_COP by 10 um on the side facing PD_MYCHIP, which drops edge density to 78% and brings every one of those isolation cells back within 8 um of the voltage-area boundary. check_mv_design (ICC2) and check_legality (ICC2) are clean after the rerun.
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