How does multi-Vt leakage recovery work in a real flow?
From PDVerse Low-Power Physical Design Mentor Guide · pdVerse Mentor Guide
Short Answer
You close timing with a low-Vt-heavy mix, then swap cells on paths with spare slack to higher-Vt versions of the same footprint, which leak far less. The implementation tool does this during optimization, and PT does it again at signoff with fix_eco_power (PT), which backs out any change that creates a timing or DRC violation. You keep a slack guard band, so later crosstalk and variation do not eat the paths you just slowed.
Technical Explanation
- Why it works: leakage falls steeply as threshold voltage rises while delay grows only moderately, so non-critical cells can afford the slower version.
- Start point: optimization reaches timing with low-Vt cells where needed, and most paths finish with slack they never use, which is leakage you pay for nothing.
- Swap rule: same footprint, different Vt, so placement and routing stay intact and only the cell reference changes.
- PT recovery:
fix_eco_power -pattern_priority {HVT SVT LVT}(PT) swaps by library name prefix, lowest-power cells listed first. - Iterative: PT makes the swaps, checks for new timing and DRC violations, and backs out the changes that caused them.
- Guard band: set a power setup margin in the ECO options so swapped paths keep a slack reserve; the value is a project choice.
- What breaks: swapping to exactly zero slack at one corner turns into violations at another corner or after crosstalk, and the ECO loop repeats.
Common Mistake
The Trap: Recovering leakage in a single-corner run with no margin, right before signoff.
- Paths swapped to near-zero slack fail in other corners or after SI, and every fix swaps cells back to low Vt.
- Run recovery across all active scenarios, or in DMSA with the worst leakage scenario named, and keep a slack reserve.
Follow-up Question & Model Response
"Why swap Vt instead of downsizing cells to save leakage?"
Candidate Model Response: Both work, and fix_eco_power (PT) can do either. A Vt swap keeps the footprint, so placement and pin access do not change, which makes it cheap late in the flow. Downsizing also cuts area and input capacitance, which saves dynamic power upstream, but it changes drive strength and can hurt transition times. Teams usually swap Vt first and downsize where slack is still left, then rerun power analysis to confirm both savings at the corner the spec names.
Practical Example
Design Scenario: (illustrative) PD_CPU closes timing at 0.9 V with 38% low-Vt cells and 4.1 mW leakage at the hot corner. Endpoints under 20 ps of slack keep LVT, those between 20 and 80 ps may take SVT, and the rest take HVT. fix_eco_power -pattern_priority {HVT SVT LVT} (PT) swaps 61,000 cells, the low-Vt share drops to 9% and leakage falls to 1.7 mW, while worst setup slack stays at +12 ps. Hold slack improves slightly on the swapped paths, since slower cells only help hold. Standby power for the phone drops by the same 2.4 mW, which matters more than any active-mode saving because the CPU cluster sits idle most of the day. The name prefixes and numbers are illustrative.
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