Walk through the complete "Mychip" multivoltage architecture — what are its power domains, and how do they relate to each other?
From PDVerse Low-Power Physical Design Mentor Guide · pdVerse Mentor Guide
Technical Explanation
Mychip is a full worked example that gives you a real four-domain chip instead of a toy two-domain sketch. PD_MYCHIP is the top-level, always-on 1.0V domain that wraps everything. Inside it sit three children: PD_CPU, an always-on 0.9V domain holding instance U_CPU; PD_COP, a 1.1V domain holding U_COP that can be fully shut down and therefore needs retention registers; and PD_DSP, a domain holding U_DSP whose supply is switched externally between 1.1V and 0.9V rather than by an on-chip switch. A Power Controller (U_PC) sits alongside these and drives the control signals that make shutdown/ retention/isolation actually happen: PSE (power switch enable), PSE_ACK (switch acknowledge), ISE (isolation enable) and SRE (save/ restore enable).
Architecture-level Reasoning
The architecture is organized the way a real chip's power intent is organized: one always-on domain at the root guarantees there is always a stable place for control logic to live, while the domains that need to save power (PD_COP) or track an externally-managed rail (PD_DSP) are carved out as children. Putting the Power Controller in the always-on domain is not incidental — it must be alive at all times to be able to wake the very domains it controls.
Step-by-step Walkthrough
1) create_power_domain PD_MYCHIP -include_scope establishes the always-on top. 2) create_power_domain PD_CPU -elements {U_CPU} and the analogous statements for PD_DSP and PD_COP create the three children by naming their instances. 3) A power-mode table (PM1-PM4) defines four power modes across these domains, and its accompanying strategy table ties PD_COP's power-switch rule to U_PC.PSE/PSE_ACK, its isolation rule to U_PC.ISE, and its retention rule to U_PC.SRE. 4) The diagram below shows the full picture: MYCHIP top containing CPU/COP(with its retention sub-block)/DSP, the power controller's PSE/PSE_ACK/ISE/SRE outputs, and the external ports PVDDdsp, PVDD0p9, PVDD1p0, PGND.
Command
create_power_domain PD_MYCHIP -include_scope
create_power_domain PD_CPU -elements {U_CPU}
create_power_domain PD_DSP -elements {U_DSP}
create_power_domain PD_COP -elements {U_COP}Switch-by-switch
-include_scope: makes the top-level domain also own the current
scope's own logic (the chip-level glue outside the three subblocks). -elements {U_CPU}/{U_DSP}/{U_COP}: names the exact instance
that forms the extent of each child domain — this is what ties a UPF
domain object to real hierarchy.Expected Result
Four cleanly separated power domains exist, with PD_CPU/PD_COP/ PD_DSP correctly nested as children of PD_MYCHIP, and the powercontroller-driven control signals (PSE, PSE_ACK, ISE, SRE) available to be wired into the switch, isolation and retention strategies of PD_COP.
Possible Implementation Error
An engineer forgets to include the Power Controller's own logic in the always-on PD_MYCHIP domain (e.g. leaves U_PC unassigned to any domain), which later fails the requirement that every domain must have exactly one primary power/ground net and that before commit_upf all instances must belong to a power domain.
Likely Tool / Clp Warning
Not committing all instances to a domain surfaces as an UPF-level 'every instance must belong to a domain' failure at commit_upf/ check_mv_design time rather than at create_power_domain time — there is no specific error code documented for this particular case.
Root Cause
A domain's extent is defined purely by the -elements list you supply; anything left out simply isn't in any domain until it is explicitly assigned.
Debugging Sequence
1) Re-read the create_power_domain statements for all four domains. 2) Confirm U_PC is inside PD_MYCHIP's extent. 3) Run check on domain completeness before commit_upf. 4) Cross-check the strategy table's rule column against the actual instance paths used in -elements. An instance left outside any power domain is a hard UPFcompleteness blocker — it must be resolved before commit_upf/ synthesis can proceed with the intended power architecture.
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