What is a secondary power pin, and which cells have one?
From PDVerse Low-Power Physical Design Mentor Guide · pdVerse Mentor Guide
Short Answer
A secondary power pin is a second supply pin on a dual-rail cell, fed from a strap other than the row rail it sits on. Always-on buffers, isolation cells, level shifters, retention flops and always-on tie cells use one because they must see a supply the row does not provide.
Technical Explanation
- A normal cell takes power from the row rail by abutment. A dual-rail cell adds a secondary PG pin for its second supply.
- Always-on buffers and retention flops in a switched area take the always-on supply on it, so they keep working when the row rail is off.
- Level shifters need both the input-side and output-side supplies; isolation cells inside a switched area need the always-on supply.
- Always-on tie cells in a switched area also take their supply from the secondary pin.
- Single-rail versions of these cells exist, but they only work where the row rail already carries the supply they need, such as an always-on area.
- The row does not carry the secondary supply, so each pin must be routed to a strap, for example with
route_group -nets(ICC2). - Place dual-rail cells far from the strap and the route has too much IR drop or EM;
create_secondary_pg_placement_constraints(ICC2) keeps them close.
Common Mistake
The Trap: Assuming the secondary pin connects by abutment like the row rail.
- It stays unconnected until routed, so the always-on buffer or retention flop loses power the moment its domain turns off.
- Run
check_pg_connectivity(ICC2) after routing: it checks physical PG connectivity down to standard-cell pins, so an unrouted secondary pin shows up as floating.
Follow-up Question & Model Response
"How does the router know which pins are secondary PG pins?"
Candidate Model Response: The library marks them. In the cell frame view, the pin must have is_secondary_pg set to true and port_type set to power or ground. If those attributes are wrong, the router treats the pin as something else and skips it. Check the attributes before routing.
Practical Example
Design Scenario: (illustrative) PD_COP runs on VDD1p0_SW. Its retention control net needs buffering, so the tool uses an always-on buffer (AOBUF_X2, an illustrative name). Its VDD pin sits on the VDD1p0_SW row rail and its VDDA secondary pin routes about 5 µm up to a VDD1p0 always-on strap, so the buffer stays alive while PD_COP is off. Before routing, check_pg_connectivity -nets VDD1p0 (ICC2) would flag VDDA as unconnected; after route_group -nets {VDD1p0} (ICC2) it should come back clean. Isolation cells placed inside PD_COP need the same VDD1p0 strap on their secondary pin.
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