How do you size a MTCMOS sleep transistor (header/footer), and what happens if it's undersized or oversized?
From PDVerse Low-Power Physical Design Mentor Guide · pdVerse Mentor Guide
Definition
Sizing an MTCMOS (multi-threshold CMOS) sleep transistor means choosing its channel width (and hence its on-resistance) so that it can supply the domain's worst-case active current with acceptably small IR-drop on the virtual rail, while keeping its own off-state leakage — since a large HVT sleep device still leaks some — small relative to the leakage it's meant to eliminate.
Mentor Explanation
The sleep transistor sits between the always-on supply and the domain's virtual rail (header, PMOS) or between the virtual ground and true ground (footer, NMOS), and while it's on it must not introduce so much series resistance that it drops a significant fraction of the supply voltage away from the logic it's feeding — that drop directly eats into the domain's timing margin, since every gate inside effectively sees a lower Vdd than the "always-on" case. Sizing is normally done by simulating (or estimating) the domain's peak simultaneous switching current, then choosing a sleep-transistor width such that the resulting IR-drop across it stays within a specified budget (commonly a few percent of Vdd) at that worst-case current — often split across many smaller distributed sleep-transistor "fingers" placed throughout the domain rather than one giant device at one corner, to avoid a large local IR-drop gradient.
Example
A high-performance CPU core domain with large simultaneous-switching current needs a much wider (or more numerous, distributed) sleep-transistor array than a small, low-activity peripheral domain — sizing is not a fixed rule of thumb, it's derived from that specific domain's actual current profile.
Why It Matters
An undersized sleep transistor causes real functional risk: excessive IR-drop degrades every timing path in the domain, potentially causing setup violations that never show up in gate-level-only timing analysis (which typically assumes an ideal supply) — this is a common source of silicon that passes STA but fails in the lab. An oversized sleep transistor wastes area and, worse, adds unnecessary sleep-transistor-own leakage during the "off" state, partially defeating the purpose of power-gating in the first place, plus it increases inrush/rush current at wake-up, which is its own separate problem (see the rush-current sequencing question).
Command
# Conceptual sizing check (not a literal EDA command, describes the analysis):
IR_drop = I_peak_domain * R_on_sleep_transistor
# choose sleep-transistor width (-> lower R_on) such that:
IR_drop <= IR_drop_budget (commonly a few % of Vdd)
# then verify: sleep_transistor_off_leakage << leakage_saved_by_gating_the_domainCommon Beginner Mistake
Treating sleep-transistor sizing as a fixed percentage rule ("make it 10% of the domain's total drive strength") applied uniformly across every domain, rather than deriving it from that specific domain's actual worst-case simultaneous switching current and the domain's own timing margin budget. Undersizing silently degrades timing margin in a way that gate-level STA (assuming an ideal always-on supply) won't catch, making it a signoff gap rather than an obvious functional bug.
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