Why does reducing supply voltage (Vdd) help reduce power, and what is the trade-off?
From PDVerse Low-Power Physical Design Mentor Guide · pdVerse Mentor Guide
Definition
Reducing supply voltage reduces power because power is a function of the square of the voltage — so even a modest voltage cut yields a much larger power reduction — but the trade-off is reduced circuit speed, since lower voltage means slower switching and less margin against process/temperature variation.
Mentor Explanation
A beginner often assumes power scales linearly with voltage, but it actually scales with V². Think of it this way: cutting Vdd by even 10% can meaningfully cut power, which is exactly why techniques like DVS/DVFS and simply running non-critical blocks at lower fixed voltages exist — they're all built on this one relationship.
Example
Voltage-scaling curves for a 45nm technology plot relative frequency against voltage from 0.88V to 1.21V across fast/typical/slow process corners, showing visually how lowering voltage pulls frequency down together with power.
Why It Matters
This relationship underlies almost every architectural low-power technique: multi-voltage domains, DVS, DVFS, and fully shutting off Vdd for power gating are all ways of exploiting the V² power relationship, at a designed-for cost in speed or complexity.
Equation
Power is proportional to the square of the voltage (P ~ V^2)Common Beginner Mistake
A beginner mistake is lowering Vdd on a critical-performance block without checking whether it can still meet its target frequency at that voltage — the whole point of DVS/ DVFS lookup tables is to only lower voltage when performance headroom allows it.
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