IntermediateQuestion 143 of 162Source: Synopsys ICC2 Implementation User Guide: Routing

What exactly does check_routability check, and what are its defaults?

From PDVerse PnR Interview Handbook · pdVerse Mentor Guide

By Tabish Iqbal · 9+ Years VLSI Physical Design Experience

Short Answer

check_routability checks that every pin can actually be reached and that the routing setup is legal before any routing starts. By default it checks blocked standard cell ports, blocked macro and top-level ports, out-of-boundary pins, minimum grid, via definitions, via cut blockages and minimum width settings. The two defaults worth remembering are the search ranges: twice the layer pitch for standard cell pins and ten times the pitch for macro and top-level pins.

A blocked standard cell pin covered by a PG strap beside an accessible pin, with the default search range of twice the layer pitch dimensioned around each. — Technical Reference DiagramWhat exactly does check_routability check, and what are its defaults?

Technical Explanation

Blocked standard cell ports: a port is blocked if no physical pin is accessible. A pin counts as accessible if any one of these holds: it contains a via up to a neighbouring layer, a path on the pin layer reaches the search range, or a shorter pin-layer path ends in a via to a neighbouring layer. The default search range is twice the layer pitch, set with -standard_cell_search_range, up to 10.
Blocked macro and top-level ports use a longer reach: a legal path must extend 10 times the layer pitch on the pin layer, or 10 pitches on the neighbouring layer reached through one via. -blocked_range and -blocked_range_via_side change these, up to 40.
Out-of-boundary pins and minimum grid violations are checked next. A pin off the gridResolution grid, or outside the block, cannot be routed cleanly.
Via definitions are always checked and cannot be turned off. Uncolored via arrays must be at most 20 rows or columns, custom or asymmetric simple vias at most 1000 cuts, and the design at most 65,535 via definitions.
Minimum width settings are also always checked: an NDR or shield width must not exceed the technology maximum width.
Layer constraints are honoured in the blocked-port checks. Global and net-specific min and max layers count as hard only when their mode options are set to hard, and -honor_layer_constraints false ignores them.
Results go to check_routability.err by default, which is saved with the block, and -max_error caps how many are reported. Further checks, such as blocked PG ports and frozen-net blocked ports, can be switched on as options.

What To Check

Blocked standard cell and macro port counts, and which cells they belong to.
Out-of-boundary and minimum grid violations.
Via definition and minimum width errors, which point at library or rule setup rather than placement.
The error data file, opened in the GUI to see where blocked pins cluster.

Command Checks & Actions

ICC2check_routability

Runs all default checks on pins, grid, via definitions and width settings.

ICC2check_routability -check_pg_blocked_ports true

Adds the optional check for PG ports that are blocked.

ICC2check_routability -standard_cell_search_range 3

Widens the standard cell pin access search to three pitches, useful when judging borderline pins.

ICC2check_routability -error_data pre_route.err

Writes the results to a named error data file you can reopen and compare later.

Healthy, Suspicious & Hard-stop Results

Healthy (illustrative): Zero blocked ports, zero out-of-boundary and grid violations, and no via definition or width errors.
Suspicious (illustrative): A handful of blocked standard cell ports under one PG strap or at one macro edge, fixable before routing.
Hard stop: Via definition or minimum width errors, or blocked macro pins. These cannot be solved by the router and must be fixed in setup or floorplan.

Common Mistake

The Trap: Turning off the standard cell blocked-port check because it reports hundreds of errors in a dense block. Those errors were real pins with no legal escape. The block routes with hundreds of opens and DRCs at those cells.

What The Interviewer Is Testing

Whether you know the default ranges and why macros get a longer one.
Do you know which checks cannot be disabled and why?
A strong answer shows you treat routability errors as floorplan or library problems rather than router problems.

Follow-up Question & Model Response

"Why does a macro pin get a ten-pitch access range while a standard cell pin gets two?"

Candidate Model Response: Standard cell pins sit inside a dense row of other cells; the router only needs a short legal stub to escape to a neighbouring layer, and a longer requirement would flag almost every pin. Macro and top-level pins connect to long nets from outside the macro, often through a crowded boundary, so they need a real path out, not just a stub. The longer range checks that a route can actually leave the pin area on the pin layer or through one via.

Practical Example

Tapeout Scenario: Before routing, check_routability reports 0 out-of-boundary pins, 0 grid violations and 23 blocked standard cell ports (illustrative). Opening the error data shows all 23 on flip-flops under an M2 PG rail extension that a script added late. Removing the extension clears them. A second run reports 4 blocked macro ports on an SRAM whose pins sit 0.1 um from a routing blockage, less than the ten-pitch access range, so the blockage is pulled back by 1 um and the check comes back clean.

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