How do routing tracks relate to pitch, and why must pins be on-grid?
From PDVerse PnR Interview Handbook · pdVerse Mentor Guide
Short Answer
Tracks are the lines a gridded router places wires on, laid out at the layer pitch, which is minimum width plus minimum spacing. A wire drawn on a track automatically keeps legal spacing from wires on the neighbouring tracks. A pin that does not line up with the track grid forces the router to jog off-grid, and those connections produce DRCs that are very hard to clean up.
Technical Explanation
- Pitch is the centre-to-centre distance between tracks on a layer. For a minimum-width wire, pitch equals minimum width plus minimum spacing, so two wires on adjacent tracks are exactly legal.
- Tracks have an offset as well as a pitch. The offset says where the first track starts, and it has to match how the standard cell library placed its pins. Cell pins are drawn so that, when the cell sits on a legal site, each pin lands on a track. Change the offset, or place a cell off its site grid, and that alignment breaks for every instance at once.
- A grid-based router snaps every segment to a track and only changes direction at track crossings. That is what makes it fast: it searches a grid, not open space.
- If a pin sits between two tracks, the router cannot land on it directly. It has to add an off-grid jog, which can crowd the neighbouring track and create spacing violations that search-and-repair struggles to resolve.
- Zroute uses a dynamic maze grid that can connect to off-grid pins while keeping gridded speed. That makes off-grid pins possible, but not free: they still cost more and are a common source of the last few stubborn DRCs.
check_routabilityreports pins off the minimum manufacturing grid and ports that sit off the routing tracks, so it catches many alignment problems before routing starts. The root fix is usually in the library or in how rows and tracks were created.- Wide wires from non-default rules use more than one track. A double-width, double-spacing clock wire effectively takes the track it sits on plus a neighbour on each side. That is why a block with many NDR nets needs more tracks than its net count suggests, and why the congestion estimate has to know about NDRs before routing.
Common Mistake
The Trap: Shifting the core origin by a fraction of a site during floorplanning without regenerating tracks. Cells still place legally, but every pin is now half a pitch off the track grid. route_auto finishes with thousands of short spacing violations at pins, and the engineer blames the router instead of the offset.
Follow-up Question & Model Response
"How would you notice an off-grid pin problem before detail routing?"
Candidate Model Response: Before routing, check_routability reports pins off the minimum grid and pins with no legal access. In the layout you can overlay the track grid on a few cells and see whether pins sit on tracks. After a trial detail route, a cluster of DRCs right at pins on many different cell types, rather than in one congested area, points strongly at a track offset problem rather than congestion.
Practical Example
Tapeout Scenario: M2 has a 0.064 um pitch and 0 offset (illustrative). A standard cell's A pin centre sits at x = 0.192, exactly on track 3, so the router lands on it with a straight wire. A new macro's pin sits at x = 0.224, halfway between tracks 3 and 4. The router has to jog off-grid to reach it, and the jog comes within 0.02 um of the wire on track 4, which is less than minimum spacing. One off-grid pin produces one violation that search-and-repair may never fully clear without moving the neighbour. Repeated across the macro's 256 pins, the block ends detail routing with hundreds of DRCs that all look like congestion but are really one alignment problem. The fix belongs in the macro abstract or its placement offset.
PnR Flow Mentor Guide
Master the Physical Design Implementation Flow
Read the complete 8-chapter PnR Flow Mentor Guide free on the web — library setup through placement, clock tree synthesis, routing, chip finishing, hierarchical implementation, and ECO, all the way to stream-out.
Continue practising