What is a strong final input-readiness checklist for physical design?
From PDVerse PnR Interview Handbook · pdVerse Mentor Guide
Short Answer
A strong input-readiness review asks whether the next implementation stage can start reproducibly with complete, consistent intent. It records evidence and ownership for unresolved issues rather than stopping at a file checklist.
Technical Explanation
Check identity and connectivity first: approved top and revision, matching libraries and macros, resolved references, expected design counts, and explained connectivity warnings. Check physical setup next: process stack, scale, sites, rows, layers, macro views, and any imported floorplan. Confirm that imported physical objects match the intended netlist. Then check timing and power intent: complete clocks and interfaces, reviewed exceptions, required modes/corners/scenarios with appropriate active analyses, matching logical and RC models, and justified electrical assumptions. For applicable designs, verify UPF application and domain crossings, scan-chain annotation and test modes, and representative switching activity for the planned power tasks. Close with reproducibility. Store a manifest of exact input paths and revisions or checksums, the tool release, setup scripts, import logs, coverage reports, and a saved initial database. Record approved exceptions with a reason, owner, affected scope, and next review point. A readiness review does not require perfect initial timing; it requires that initial violations are meaningful and the implementation problem is correctly defined.
Common Mistake
Demanding zero timing violations before placement, while ignoring missing constraints or undocumented input substitutions.
Follow-up Question & Model Response
How would you summarize this in an interview? 'I verify what is loaded, what it applies to, which operating cases are checked, and whether someone else can reproduce the same initial design.'
Practical Example
The team accepts initial negative setup slack because timing optimization is the next step, but rejects an unconstrained input bus and missing SRAM slow-corner model. The first is a valid optimization target; the latter two undermine the analysis itself.
Continue practising