How can a design pass LVS but fail ERC?

Short Answer

LVS only asks whether the layout matches the reference netlist. If the reference itself contains an electrical hazard, such as an unused gate input left unconnected, the layout faithfully reproduces it and LVS passes. ERC checks the extracted circuit for hazards like floating gates, so it fails on exactly the case LVS cannot see.

Technical Explanation

• A floating gate has no driver and no tie to a supply. Its voltage drifts with leakage and coupling, often settling near the switching threshold. At that point both the pull-up and pull-down transistors of the next stage are partly on, and current flows straight from VDD to VSS.
• If the RTL or netlist leaves a spare-cell input or an unused mux input unconnected, and the layout also leaves it unconnected, both netlists agree. The compare() (ICV) result is PASS because there is nothing to mismatch.
• ERC does not compare. It walks the extracted connectivity and applies electrical rules from the runset, such as "every gate must connect to a driver or a supply" and "every well must be tied". A floating input fails that rule directly.
• The effect in silicon is leakage and noise. One floating input may add microamps; a spare-cell array with hundreds of floating inputs can move standby current enough to fail a low-power specification, and a floating input on a live path can cause random logic values.
• Other pass-LVS, fail-ERC cases include wells or substrate regions without a tap connection and gates tied directly to a supply rail where the foundry requires a tie-high or tie-low cell for protection. The netlist may express the tie the same way in both views, so LVS is happy.
• ERC is not a separate tool. The IC Validator guide lists ERC alongside DRC and LVS as checks a runset can contain, and the foundry decides which electrical rules are included and whether they run with the LVS extraction or in their own deck. Read the foundry runset notes to know which ERC checks your signoff actually covers.
• The usual fix is in the netlist, not the layout: tie unused inputs through tie cells, then rerun LVS and ERC. Changing only the layout would make LVS fail, because the reference would still show the input unconnected.

Follow-up Question & Model Response

"Why does fixing the floating input usually need a netlist change rather than a layout-only change?"

Candidate Model Response: LVS compares the layout with the reference netlist. If I just draw a connection from the floating input to a tie cell in the layout, the reference still shows the input unconnected, so LVS now fails on an extra connection. The correct fix is an ECO in the netlist that connects the input to a tie-high or tie-low cell, then the matching layout change. After that both LVS and ERC pass on the same data.