The grid is too weak in one region. What fixes exist?
From PDVerse PnR Interview Handbook · pdVerse Mentor Guide
Short Answer
You either lower the resistance between the taps and the weak cells or lower the current they draw at once. The grid options are wider straps, extra straps or via stacks, and PG augmentation, where signoff_create_pg_augmentation (ICC2) uses a RedHawk Fusion voltage drop result to add PG shapes in free space through IC Validator. In standalone RedHawk, mesh fix (RH) and mesh optimize (RH), driven by GSR keywords, work out new strap widths and write an ECO file that still has to be implemented in the layout.
Technical Explanation
- Widening straps lowers resistance along them and costs the routing tracks beside them. Extra straps shorten the path to each cell, and more vias fix resistance at layer changes, often where the drop builds up.
- PG augmentation adds metal shapes that act as parallel resistors and lower the grid resistance the cells see. ICC2 offers standard augmentation (as many shapes as possible), timing-driven augmentation (avoiding timing-critical nets), and guided augmentation with
fix_pg_wire(ICC2), which adds shapes only from IR-violating cells to their tap with the minimum path resistance. - Standard augmentation needs a routed block with very few DRC violations, an IC Validator licence, a voltage drop run first,
signoff.create_pg_augmentation.power_net_name(ICC2) andsignoff.create_pg_augmentation.ground_net_name(ICC2) set,save_block(ICC2) because IC Validator reads the on-disk block, and-node(ICC2) on the command. A design with more than one power net needs one run per net, with-mode add(ICC2) on the later runs. - Timing-driven augmentation takes
-nets(ICC2) or-timing_preserve_setup_slack_threshold(ICC2) and by default removes existing augmentation shapes first unless you give-mode add(ICC2). - In RedHawk,
mesh fix(RH) looks for a width solution around each hotspot in fao_region, resizing wires in bands through each fix window (default 100u x 100u) across the chip, unless-taper(RH) keeps changes inside the region.mesh optimize(RH) sizes all wires on the chosen layers uniformly, andmesh vias(RH) adds optimal vias. - The manual recommends
mesh snscalc(RH) before any resizing. It reports mV of drop reduction per micron of added width, by layer and net. - The current side is often cheaper: spread high-power cells, move clustered clock buffers apart, add decap for dynamic drop, or reduce activity. Decap helps dynamic drop and does nothing for static drop.
What To Check
- Whether the problem is static (resistance) or dynamic (current bursts), since the fixes differ.
- Minimum path resistance of the hot cells: one high-resistance path points to vias rather than strap width.
- Routing tracks and timing near any metal you add.
- Drop after the fix, measured by rerunning the same analysis on the same scenario.
- Signoff DRC after augmentation.
Command Checks & Actions
analyze_rail -voltage_drop static -nets {VDD VSS}Voltage drop result that augmentation uses as its guide; rerun afterwards to measure the gain.
set_app_options -name signoff.create_pg_augmentation.power_net_name -value VDDNames the power net to augment; the ground net option is set the same way.
save_blockSaves the block to disk, which is what IC Validator reads.
signoff_create_pg_augmentation -node <node>Adds PG augmentation shapes for the technology node given by -node.
mesh snscalcReports drop reduction per micron of extra width, by layer and net, before any resizing.
mesh fix -eco mesh_fix.ecoFinds strap widths that fix the hotspots and writes an ECO file.
Healthy, Suspicious & Hard-stop Results
- Healthy (illustrative): Worst static drop goes from 41 mV to 27 mV against a 36 mV budget, with no new DRC errors and WNS within 2 ps of before.
- Suspicious (illustrative): Drop improves by less than 10% after augmentation, which suggests the resistance sits in vias or the current is the real problem.
- Hard stop: New DRC errors or lost setup slack on critical nets, or drop still over budget with no routing space left.
Common Mistake
The Trap: Widening every M6 strap in the region because the map is red there, when minimum path resistance shows the cells reach the grid through a single V1 stack on each rail. The wider straps take 40 routing tracks, congestion rises, and the drop falls by only 2 mV because the straps were never the bottleneck.
What The Interviewer Is Testing
- Separating resistance fixes from current fixes.
- Knowing the augmentation prerequisites: routed block, voltage drop first, net options,
save_block(ICC2) and the IC Validator licence. - Knowing RedHawk mesh commands produce an ECO file that still has to be implemented.
Follow-up Question & Model Response
"Why rerun voltage drop after augmentation instead of trusting the tool?"
Candidate Model Response: Augmentation inserts as much as the rules allow, but the gain depends on where the shapes landed relative to the hot cells. The guide's own flow ends with a second voltage drop run to measure the result. The added metal also changes coupling, so I rerun timing on nearby nets.
Practical Example
Tapeout Scenario: A 0.8 V block (illustrative) shows a static hotspot of 41 mV against a 4.5% budget of 36 mV. mesh snscalc (RH) on the standalone database shows M5 worth 0.9 mV per um of extra width and M7 only 0.2 mV per um. Minimum path resistance shows no single-via bottleneck. Standard augmentation on VDD and VSS adds 3,200 metal and 5,900 via shapes in unused space, and the rerun gives 27 mV worst. Setup WNS moves from +11 ps to +9 ps and signoff DRC is clean.
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